Can't generate xsa for kv260

Win10 xilinx 2022.1, When I run 'make xsa' command I get the following error:

kria-vitis-platforms\kv260\platforms\vivado\kv260_vcuDecode_vmixDP>make xsa
/bin/vivado -mode batch -notrace -source scripts/main.tcl -tclargs -jobs 8
process_begin: CreateProcess(NULL, sh.exe -c "/bin/vivado -mode batch -notrace -source scripts/main.tcl -tclargs -jobs 8", ...) failed.
make (e=2): The system cannot find the file specified.
make: *** [Makefile:29: project/kv260_vcuDecode_vmixDP.xsa] Error 2

I added the path to sh.exe from git installation into my PC paths and now the error message has changed to the following:

kria-vitis-platforms\kv260\platforms\vivado\kv260_vcuDecode_vmixDP>make xsa
/bin/vivado -mode batch -notrace -source scripts/main.tcl -tclargs -jobs 8
/usr/bin/bash: /bin/vivado: No such file or directory
make: *** [Makefile:29: project/kv260_vcuDecode_vmixDP.xsa] Error 127

After adding XILINX_VIVADO env variable with the path to vivado main folder, the script does run... but

kv260\platforms\vivado\kv260_vcuDecode_vmixDP> make xsa
C:\Xilinx\Vivado\2022.1/bin/vivado -mode batch -notrace -source scripts/main.tcl -tclargs -jobs 8

****** Vivado v2022.1.2 (64-bit)
**** SW Build 3605665 on Fri Aug  5 22:53:37 MDT 2022
**** IP Build 3603185 on Sat Aug  6 04:07:44 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source scripts/main.tcl -notrace
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at C:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2022.1/data/ip'.
Wrote  : <C:\Work\xpltfrms\kv260\platforms\vivado\kv260_vcuDecode_vmixDP\project\kv260_vcuDecode_vmixDP.srcs\sources_1\bd\kv260_vcuDecode_vmixDP\kv260_vcuDecode_vmixDP.bd>
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
create_bd_cell: Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1731.723 ; gain = 448.383
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_DIVCLK_DIVIDE' from '7' to '13' has been ignored for IP 'display_pipeline/clk_wiz_0'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKFBOUT_MULT_F' from '64.375' to '59.000' has been ignored for IP 'display_pipeline/clk_wiz_0'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKOUT0_DIVIDE_F' from '3.500' to '4.750' has been ignored for IP 'display_pipeline/clk_wiz_0'
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'GEN_F0_VSYNC_HSTART' from '2008' to '1004' has been ignored for IP 'display_pipeline/v_tc_0'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'GEN_F0_VSYNC_HEND' from '2008' to '1004' has been ignored for IP 'display_pipeline/v_tc_0'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'GEN_F0_VBLANK_HSTART' from '2008' to '960' has been ignored for IP 'display_pipeline/v_tc_0'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'GEN_F0_VBLANK_HEND' from '2008' to '960' has been ignored for IP 'display_pipeline/v_tc_0'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'GEN_F1_VSYNC_HSTART' from '2008' to '1004' has been ignored for IP 'display_pipeline/v_tc_0'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'GEN_F1_VSYNC_HEND' from '2008' to '1004' has been ignored for IP 'display_pipeline/v_tc_0'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'GEN_F1_VBLANK_HSTART' from '2008' to '960' has been ignored for IP 'display_pipeline/v_tc_0'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'GEN_F1_VBLANK_HEND' from '2008' to '960' has been ignored for IP 'display_pipeline/v_tc_0'
WARNING: [BD 41-1306] The connection to interface pin </display_pipeline/v_axi4s_vid_out_0/vid_active_video> is being overridden by the user with net <v_axi4s_vid_out_0_vid_active_video>. This pin will not be connected as a part of interface connection <vid_io_out>.
WARNING: [BD 41-1306] The connection to interface pin </display_pipeline/v_axi4s_vid_out_0/vid_data> is being overridden by the user with net <v_axi4s_vid_out_0_vid_data>. This pin will not be connected as a part of interface connection <vid_io_out>.
WARNING: [BD 41-1306] The connection to interface pin </display_pipeline/v_axi4s_vid_out_0/vid_hsync> is being overridden by the user with net <v_axi4s_vid_out_0_vid_hsync>. This pin will not be connected as a part of interface connection <vid_io_out>.
WARNING: [BD 41-1306] The connection to interface pin </display_pipeline/v_axi4s_vid_out_0/vid_vsync> is being overridden by the user with net <v_axi4s_vid_out_0_vid_vsync>. This pin will not be connected as a part of interface connection <vid_io_out>.
WARNING: [BD 41-1306] The connection to interface pin </display_pipeline/v_mix_0/s_axis_video_TDATA> is being overridden by the user with net <xlconstant_0_dout>. This pin will not be connected as a part of interface connection <s_axis_video>.
WARNING: [BD 41-1306] The connection to interface pin </display_pipeline/v_mix_0/s_axis_video_TVALID> is being overridden by the user with net <xlconstant_0_dout>. This pin will not be connected as a part of interface connection <s_axis_video>.
WARNING: [BD 5-236] No ports matched 'get_bd_ports fan_en_b'
WARNING: [BD 5-235] No pins matched 'get_bd_pins PS_0/emio_ttc0_wave_o'
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [xilinx.com:ip:vcu:1.2-17] /vcu/vcu_0: Init
WARNING: [BD 41-1306] The connection to interface pin </PS_0/emio_gpio_o> is being overridden by the user with net <PS_0_emio_gpio_o>. This pin will not be connected as a part of interface connection <GPIO_0>.
Slave segment '/axi_vip_0/S_AXI/Reg' is being assigned into address space '/PS_0/Data' at <0xA000_0000 [ 64K ]>.
Slave segment '/display_pipeline/clk_wiz_0/s_axi_lite/Reg' is being assigned into address space '/PS_0/Data' at <0x8000_0000 [ 64K ]>.
Slave segment '/display_pipeline/v_mix_0/s_axi_CTRL/Reg' is being assigned into address space '/PS_0/Data' at <0xB000_0000 [ 64K ]>.
Slave segment '/display_pipeline/v_tc_0/ctrl/Reg' is being assigned into address space '/PS_0/Data' at <0x8001_0000 [ 64K ]>.
Slave segment '/vcu/vcu_0/S_AXI_LITE/Reg' is being assigned into address space '/PS_0/Data' at <0x8010_0000 [ 1M ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/display_pipeline/v_mix_0/Data_m_axi_mm_video1' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/display_pipeline/v_mix_0/Data_m_axi_mm_video2' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/display_pipeline/v_mix_0/Data_m_axi_mm_video3' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/display_pipeline/v_mix_0/Data_m_axi_mm_video4' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/display_pipeline/v_mix_0/Data_m_axi_mm_video5' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP5/HP3_DDR_LOW' is being assigned into address space '/vcu/vcu_0/Code' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP1/HPC1_DDR_LOW' is being assigned into address space '/vcu/vcu_0/DecData0' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP1/HPC1_DDR_LOW' is being assigned into address space '/vcu/vcu_0/DecData1' at <0x0000_0000 [ 2G ]>.
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter In2_width(4) on '/display_pipeline/xlconcat_0' with propagated value(16). Command ignored
WARNING: [IP_Flow 19-4684] Expected long value for param HDL_PLL_CLK_LO but, float/scientific notation value 0.0 is provided. The value is converted to long type(0)
WARNING: [IP_Flow 19-4684] Expected long value for param HDL_PLL_CLK_HI but, float/scientific notation value 50.0 is provided. The value is converted to long type(50)
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_vcuDecode_vmixDP_vcu_0_0:  in flao2hex  update method .. 0.0
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_vcuDecode_vmixDP_vcu_0_0:  in HDL_AXI_ENC_CLK  update method ..0
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_vcuDecode_vmixDP_vcu_0_0:  in HDL_AXI_DEC_CLK  update method ..0
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_vcuDecode_vmixDP_vcu_0_0:  in flao2hex  update method .. 2.75
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_vcuDecode_vmixDP_vcu_0_0:  in HDL_AXI_MCU_CLK  update method ..1076887552
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_vcuDecode_vmixDP_vcu_0_0:  in flao2hex  update method .. 2.74
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_vcuDecode_vmixDP_vcu_0_0:  in HDL_AXI_MCU_CLK  update method ..1076845608
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /display_pipeline/clk_wiz_0 clk_wiz propagate
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
INFO: [xilinx.com:ip:vcu:1.2-17] /vcu/vcu_0:Pre-Propagate  .
INFO: [xilinx.com:ip:vcu:1.2-17] /vcu/vcu_0: Post Propogate  .
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_ic_ctrl_1/s00_couplers/auto_pc/S_AXI(0) and /PS_0/M_AXI_HPM1_FPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_ic_ctrl_1/s00_couplers/auto_pc/S_AXI(0) and /PS_0/M_AXI_HPM1_FPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_ic_ctrl_0/s00_couplers/auto_pc/S_AXI(0) and /PS_0/M_AXI_HPM0_LPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_ic_ctrl_0/s00_couplers/auto_pc/S_AXI(0) and /PS_0/M_AXI_HPM0_LPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /PS_0/S_AXI_HP0_FPD(1) and /display_pipeline/axi_interconnect_0/xbar/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /PS_0/S_AXI_HP0_FPD(1) and /display_pipeline/axi_interconnect_0/xbar/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /PS_0/S_AXI_HPC1_FPD(1) and /vcu/axi_reg_slice_vdec/M_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /PS_0/S_AXI_HPC1_FPD(1) and /vcu/axi_reg_slice_vdec/M_AXI(0)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /PS_0/S_AXI_HP3_FPD(1) and /vcu/axi_reg_slice_vmcu/M_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /PS_0/S_AXI_HP3_FPD(1) and /vcu/axi_reg_slice_vmcu/M_AXI(0)
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/display_pipeline/xlslice_ttc_0/Din
WARNING: [BD 41-597] NET <zynq_ultra_ps_e_0_emio_ttc0_wave_o> has no source
Wrote  : <C:\Work\xpltfrms\kv260\platforms\vivado\kv260_vcuDecode_vmixDP\project\kv260_vcuDecode_vmixDP.srcs\sources_1\bd\kv260_vcuDecode_vmixDP\kv260_vcuDecode_vmixDP.bd>
INFO: [BD 41-1662] The design 'kv260_vcuDecode_vmixDP.bd' is already validated. Therefore parameter propagation will not be re-run.
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/display_pipeline/xlslice_ttc_0/Din
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/m_axi_bid'(4) to pin: '/display_pipeline/axi_interconnect_0/m00_couplers/S_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/m_axi_rid'(4) to pin: '/display_pipeline/axi_interconnect_0/m00_couplers/S_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S00_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S00_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S01_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S01_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S02_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S02_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S03_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S03_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S04_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S04_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/display_pipeline/xlconcat_0/In2'(4) to pin '/display_pipeline/xlconstant_2/dout'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
WARNING: [BD 41-166] Source port for the net:zynq_ultra_ps_e_0_emio_ttc0_wave_o is NULL! Connection will be grounded!
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_mmu/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/S_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_mmu/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/S_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_mmu/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/S_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_mmu/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/S_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vdec/m_axi_bid'(5) to pin: '/vcu/M_AXI_DEC_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vdec/m_axi_rid'(5) to pin: '/vcu/M_AXI_DEC_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vmcu/m_axi_bid'(3) to pin: '/vcu/M_AXI_MCU_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vmcu/m_axi_rid'(3) to pin: '/vcu/M_AXI_MCU_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp1_awid'(6) to pin: '/vcu/M_AXI_DEC_awid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp1_arid'(6) to pin: '/vcu/M_AXI_DEC_arid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_awid'(6) to pin: '/display_pipeline/M00_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_arid'(6) to pin: '/display_pipeline/M00_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp5_awid'(6) to pin: '/vcu/M_AXI_MCU_awid'(3) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp5_arid'(6) to pin: '/vcu/M_AXI_MCU_arid'(3) - Only lower order bits will be connected.
Verilog Output written to : C:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/synth/kv260_vcuDecode_vmixDP.v
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/m_axi_bid'(4) to pin: '/display_pipeline/axi_interconnect_0/m00_couplers/S_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/m_axi_rid'(4) to pin: '/display_pipeline/axi_interconnect_0/m00_couplers/S_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S00_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S00_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S01_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S01_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S02_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S02_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S03_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S03_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S04_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S04_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/display_pipeline/xlconcat_0/In2'(4) to pin '/display_pipeline/xlconstant_2/dout'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
WARNING: [BD 41-166] Source port for the net:zynq_ultra_ps_e_0_emio_ttc0_wave_o is NULL! Connection will be grounded!
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_mmu/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/S_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_mmu/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/S_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_mmu/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/S_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_mmu/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/S_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vdec/m_axi_bid'(5) to pin: '/vcu/M_AXI_DEC_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vdec/m_axi_rid'(5) to pin: '/vcu/M_AXI_DEC_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vmcu/m_axi_bid'(3) to pin: '/vcu/M_AXI_MCU_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vmcu/m_axi_rid'(3) to pin: '/vcu/M_AXI_MCU_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp1_awid'(6) to pin: '/vcu/M_AXI_DEC_awid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp1_arid'(6) to pin: '/vcu/M_AXI_DEC_arid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_awid'(6) to pin: '/display_pipeline/M00_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_arid'(6) to pin: '/display_pipeline/M00_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp5_awid'(6) to pin: '/vcu/M_AXI_MCU_awid'(3) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp5_arid'(6) to pin: '/vcu/M_AXI_MCU_arid'(3) - Only lower order bits will be connected.
INFO: [Common 17-14] Message 'BD 41-2384' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Verilog Output written to : C:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/sim/kv260_vcuDecode_vmixDP.v
Verilog Output written to : C:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/hdl/kv260_vcuDecode_vmixDP_wrapper.v
INFO: [Project 1-1716] Could not find the wrapper file ./project/kv260_vcuDecode_vmixDP.srcs/sources_1/bd/kv260_vcuDecode_vmixDP/hdl/kv260_vcuDecode_vmixDP_wrapper.v, checking in project .gen location instead.
INFO: [Vivado 12-12391] Found file ./project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/hdl/kv260_vcuDecode_vmixDP_wrapper.v, importing it to Project
INFO: [BD 5-320] Validate design is not run, since the design is already validated.
INFO: [BD 41-1662] The design 'kv260_vcuDecode_vmixDP.bd' is already validated. Therefore parameter propagation will not be re-run.
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/display_pipeline/xlslice_ttc_0/Din
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/m_axi_bid'(4) to pin: '/display_pipeline/axi_interconnect_0/m00_couplers/S_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/m_axi_rid'(4) to pin: '/display_pipeline/axi_interconnect_0/m00_couplers/S_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S00_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S00_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S01_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S01_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S02_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S02_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S03_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S03_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S04_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S04_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/display_pipeline/xlconcat_0/In2'(4) to pin '/display_pipeline/xlconstant_2/dout'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
WARNING: [BD 41-166] Source port for the net:zynq_ultra_ps_e_0_emio_ttc0_wave_o is NULL! Connection will be grounded!
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_mmu/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/S_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_mmu/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/S_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_mmu/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/S_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_mmu/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/S_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vdec/m_axi_bid'(5) to pin: '/vcu/M_AXI_DEC_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vdec/m_axi_rid'(5) to pin: '/vcu/M_AXI_DEC_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vmcu/m_axi_bid'(3) to pin: '/vcu/M_AXI_MCU_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vmcu/m_axi_rid'(3) to pin: '/vcu/M_AXI_MCU_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp1_awid'(6) to pin: '/vcu/M_AXI_DEC_awid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp1_arid'(6) to pin: '/vcu/M_AXI_DEC_arid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_awid'(6) to pin: '/display_pipeline/M00_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_arid'(6) to pin: '/display_pipeline/M00_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp5_awid'(6) to pin: '/vcu/M_AXI_MCU_awid'(3) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp5_arid'(6) to pin: '/vcu/M_AXI_MCU_arid'(3) - Only lower order bits will be connected.
Verilog Output written to : C:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/synth/kv260_vcuDecode_vmixDP.v
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_awid'(4) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/M_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/s_axi_arid'(4) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/M_AXI_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/m_axi_bid'(4) to pin: '/display_pipeline/axi_interconnect_0/m00_couplers/S_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/xbar/m_axi_rid'(4) to pin: '/display_pipeline/axi_interconnect_0/m00_couplers/S_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S00_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S00_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s00_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s00_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S01_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S01_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s01_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s01_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S02_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S02_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s02_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s02_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S03_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S03_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s03_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s03_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/s_axi_arlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S04_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/s_axi_awlock'(1) to pin: '/display_pipeline/axi_interconnect_0/S04_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/m_axi_rid'(1) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/S_AXI_rid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/display_pipeline/axi_interconnect_0/s04_mmu/m_axi_bid'(1) to pin: '/display_pipeline/axi_interconnect_0/s04_couplers/S_AXI_bid'(4) - Only lower order bits will be connected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/display_pipeline/xlconcat_0/In2'(4) to pin '/display_pipeline/xlconstant_2/dout'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
WARNING: [BD 41-166] Source port for the net:zynq_ultra_ps_e_0_emio_ttc0_wave_o is NULL! Connection will be grounded!
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_mmu/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/S_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_mmu/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/S_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_mmu/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/S_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_mmu/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/S_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vdec/m_axi_bid'(5) to pin: '/vcu/M_AXI_DEC_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vdec/m_axi_rid'(5) to pin: '/vcu/M_AXI_DEC_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vmcu/m_axi_bid'(3) to pin: '/vcu/M_AXI_MCU_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_reg_slice_vmcu/m_axi_rid'(3) to pin: '/vcu/M_AXI_MCU_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp1_awid'(6) to pin: '/vcu/M_AXI_DEC_awid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp1_arid'(6) to pin: '/vcu/M_AXI_DEC_arid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_awid'(6) to pin: '/display_pipeline/M00_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_arid'(6) to pin: '/display_pipeline/M00_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp5_awid'(6) to pin: '/vcu/M_AXI_MCU_awid'(3) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp5_arid'(6) to pin: '/vcu/M_AXI_MCU_arid'(3) - Only lower order bits will be connected.
INFO: [Common 17-14] Message 'BD 41-2384' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Verilog Output written to : C:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/sim/kv260_vcuDecode_vmixDP.v
Verilog Output written to : C:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/hdl/kv260_vcuDecode_vmixDP_wrapper.v
INFO: [xilinx.com:ip:zynq_ultra_ps_e:3.4-0] kv260_vcuDecode_vmixDP_PS_0_0:
Changes in your design (including the PCW configuration settings) are not automatically exported from Vivado to Xilinx's SDK, Petalinux or Yocto.
This is by design to avoid disrupting existing embedded development efforts. To have any changes of your design taking effect in the embedded software flow please export your
design by going through Vivado's main menu, click on File, then Export finally select Export Hardware, please ensure you click on the Include BitStream option.
The auto-generated HDF file is all you need to import in Xilinx's SDK, Petalinux or Yocto for your changes to be reflected in the Embedded Software Flow.
For more information, please consult PG201, section: Exporting PCW Settings to Embedded Software Flows
INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM1_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_LPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HPC0_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HPC1_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP0_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP1_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP2_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP3_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_LPD'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block PS_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ic_ctrl_0/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/ip/kv260_vcuDecode_vmixDP_auto_pc_0/kv260_vcuDecode_vmixDP_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ic_ctrl_0/s00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/ip/kv260_vcuDecode_vmixDP_auto_pc_1/kv260_vcuDecode_vmixDP_auto_pc_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ic_ctrl_1/s00_couplers/auto_pc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_vip_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/axi_interconnect_0/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/axi_interconnect_0/s00_mmu .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/axi_interconnect_0/s01_mmu .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/axi_interconnect_0/s02_mmu .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/axi_interconnect_0/s03_mmu .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/axi_interconnect_0/s04_mmu .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/ip/kv260_vcuDecode_vmixDP_axis_subset_converter_0_0/kv260_vcuDecode_vmixDP_axis_subset_converter_0_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/axis_subset_converter_0 .
ERROR: [Common 17-680] Path length exceeds 260-Byte maximum allowed by Windows: c:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/ip/kv260_vcuDecode_vmixDP_clk_wiz_0_1/axi_lite_ipif_v1_01_a/hdl/src/vhdl/kv260_vcuDecode_vmixDP_clk_wiz_0_1_address_decoder.vhd
Please consider using the OS subst command to shorten the path length by mapping part of the path to a virtual drive letter. See Answer Record AR52787 for more information.
Resolution: In Windows 7 or later, the mklink command can also be used to create a symbolic link and shorten the path.
ERROR: [Ipptcl 7-5] XIT evaluation error: Invalid file name: c:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/ip/kv260_vcuDecode_vmixDP_clk_wiz_0_1/axi_lite_ipif_v1_01_a/hdl/src/vhdl/kv260_vcuDecode_vmixDP_clk_wiz_0_1_address_decoder.vhd
ERROR: [Common 17-39] 'xit::add_ipfile' failed due to earlier errors.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2022.1/data/ip/xilinx/clk_wiz_v6_0/ttcl/address_decoder_vhd.ttcl': ERROR: [Common 17-39] 'xit::add_ipfile' failed due to earlier errors.
ERROR: [Common 17-680] Path length exceeds 260-Byte maximum allowed by Windows: c:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/ip/kv260_vcuDecode_vmixDP_clk_wiz_0_1/axi_lite_ipif_v1_01_a/hdl/src/vhdl/kv260_vcuDecode_vmixDP_clk_wiz_0_1_slave_attachment.vhd
Please consider using the OS subst command to shorten the path length by mapping part of the path to a virtual drive letter. See Answer Record AR52787 for more information.
Resolution: In Windows 7 or later, the mklink command can also be used to create a symbolic link and shorten the path.
ERROR: [Ipptcl 7-5] XIT evaluation error: Invalid file name: c:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/ip/kv260_vcuDecode_vmixDP_clk_wiz_0_1/axi_lite_ipif_v1_01_a/hdl/src/vhdl/kv260_vcuDecode_vmixDP_clk_wiz_0_1_slave_attachment.vhd
ERROR: [Common 17-39] 'xit::add_ipfile' failed due to earlier errors.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2022.1/data/ip/xilinx/clk_wiz_v6_0/ttcl/slave_attachment_vhd.ttcl': ERROR: [Common 17-39] 'xit::add_ipfile' failed due to earlier errors.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'display_pipeline/clk_wiz_0'. Failed to generate 'Synthesis' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'display_pipeline/clk_wiz_0'. Failed to generate 'Synthesis' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block display_pipeline/clk_wiz_0
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/proc_sys_reset_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/v_axi4s_vid_out_0 .
WARNING: [IP_Flow 19-1971] File named "sim/kv260_vcuDecode_vmixDP_v_mix_0_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/v_mix_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/v_tc_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/xlconcat_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/xlconstant_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/xlconstant_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/xlconstant_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/xlslice_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/xlslice_15to8 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/xlslice_7to0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block display_pipeline/xlslice_ttc_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_100MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_275MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_550MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_interconnect_vcu_dec/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_interconnect_vcu_dec/s00_mmu .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_interconnect_vcu_dec/s01_mmu .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_reg_slice_vdec .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_reg_slice_vmcu .
FAMILY is zynquplus
DEVICE is xck26
PACKAGE is sfvc784
SPEEDGRADE is -2LV
SILICON_REVISION is
TEMPERATURE_GRADE is C
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/vcu_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/xlslice_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlslice_ttc_0 .
Exporting to file C:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/hw_handoff/kv260_vcuDecode_vmixDP.hwh
Generated Hardware Definition File C:/Work/xpltfrms/kv260/platforms/vivado/kv260_vcuDecode_vmixDP/project/kv260_vcuDecode_vmixDP.gen/sources_1/bd/kv260_vcuDecode_vmixDP/synth/kv260_vcuDecode_vmixDP.hwdef
generate_target: Time (s): cpu = 00:00:54 ; elapsed = 00:00:56 . Memory (MB): peak = 2189.391 ; gain = 86.414
ERROR: [Common 17-39] 'generate_target' failed due to earlier errors.
while executing

"generate_target all [get_files $proj_dir/${proj_name}.srcs/sources_1/bd/$proj_name/${proj_name}.bd]"
(file "scripts/main.tcl" line 59)
INFO: [Common 17-206] Exiting Vivado at Mon Nov 28 12:04:48 2022...
make: *** [Makefile:29: project/kv260_vcuDecode_vmixDP.xsa] Error 1

As seen above, why are there so many errors and warnings?

I've figured out the problem...
The issue is related to the 260 character path length limit in all xilinx tools.
So instead of attempting to generate the xsa in the git clone working folder on your local machine, copy the specific platform to maybe directly to c drive. and rename the platform folder to something small like tst or prj
This allows me to complete the process in its entireity and without any failures.

@ChillPillzKillzBillz glad you figured it out already. Indeed there is a path limitation issue which is specific to Windows, not the Xilinx tools. Running the Xilinx tools on Linux, you won't face this issue.
https://support.xilinx.com/s/article/52787?language=en_US


Why MXNet update parameters according to the key in dist_async？

Traditional asynchronous, parameter server update the model parameter as a whole, but MXNet update parameter according to the key, in the case of multimachine, this way will lead to the case a worker pull down the model parameters but its keys are not the same version, why MXNet implement dist_async in this way? The model convergence can be better?

@piiswrong @mli

This issue is closed due to lack of activity in the last 90 days. Feel free to reopen if this is still an active issue. Thanks!


"ds_train_bert_nvidia_data_bsz64k_seq128.sh" program stalls at the end of the first epoch

When I run "ds_train_bert_nvidia_data_bsz64k_seq128.sh". It stalls at the end of the first epoch.

met the same problem

Met the same problem with DeepSpeed v0.6.1.


composability issue with class based hocs

This issue aligns with https://github.com/zanettin/incompose/issues/23
I've been using the library in production for a pretty decent amount of time (big thanks for this 👍🏻). But I've ran into composability issues occasionally.
Such issues occur when consumer tries to compose multiple hocs one of which has "class" as a return value while other ones attempt to use it as a function.
For clarity here are some hocs that return "classes": withReducer, withPropsOnChange, withLifecycle
If you'll try to compose those with other hocs such as withProps or withHandlers you'll run into issue.
An example bellow will fail as https://github.com/zanettin/incompose/issues/23
const Composed = compose(
  withProps({ foo: 'bar'  }),
  withPropsOnChange(() => true, props => props),
)(() => Template);

Next one will fail Uncaught TypeError: Cannot set property 'state' of undefined
const Composed = compose(
  withProps({ foo: 'bar'  }),
  withLifecycle({ componentDidMount: () => console.log('Hello') }),
)(() => Template);

I've expected those functions to works nicely together.
Please, correct me if I am wrong or missing the point behind this library design.
I think there are two way we can approach this issue.

Either by updating first set of hocs in the same manner as in https://github.com/zanettin/incompose/issues/23

With this solution we kinda set a convention that every input component in composition should be functional. The drawback - we have to care about it manually

update another set of hocs replacing component function expressions into jsx (Component({ ...config, ...props }) into <Component {...config} {...props} />) or by using createElement Inferno API

With this solution we delegate the issues to Inferno layer
Let me know which solution you think is more preferable?

Hi @ioi0
Thanks again for the kind words and your inputs.
haven't worked with inferno for a while so i've missed some updates on the core 🙈  regarding your questions: yes, they should (still) be composable and yes, the JSX pattern is the one i'd go with.
i've started a new PR (#27 ) over there and played around with almost all available HoCs and it does work so far. my test code can be found below:
import {
  compose,
  withProps,
  withPropsOnChange,
  withLifecycle,
  withHandlers,
  branch,
  renderComponent,
  defaultProps,
  flattenProps,
  mapProps,
  renameProp,
  renameProps,
  withState,
  shouldUpdate
} from "incompose";
import { linkEvent } from "incompose/node_modules/inferno";

const App = () => null;

const inc = props => props.setCounter(props.counter + 1);

const Counter = props => (

counter: {props.counter}

    <button onClick={linkEvent(props, inc)}>+</button>

);

export default compose(
  withState("counter", "setCounter", 1),
  withProps({
    foo: "bar",
    person: { firstName: "John", lastName: "Doe", age: 33 },
    price: 200,
    discount: 20
  }),
  defaultProps({ foo: 123, bar: 321 }), // should not override withProps
  flattenProps("person"),
  mapProps(({ price, discount, ...props }) => ({
    discountPrice: price - discount,
    ...props
  })),
  renameProp("firstName", "first-name"),
  renameProps({ lastName: "last-name", age: "a-g-e" }),
  withPropsOnChange(() => true, props => props),
  withLifecycle({
    componentDidMount: () => console.log("did mount"),
    componentWillMount: () => console.log("will mount"),
    componentDidUpdate: () => console.log("did update"),
    componentWillUpdate: () => console.log("will update"),
    componentWillUnmount: () => console.log("will unmount")
  }),
  withHandlers({
    getRandomValue: _ => Math.floor(Math.random() * 1000)
  }),
  shouldUpdate((props, nextProps) => {
    console.warn("props", props);
    console.warn("nextProps", nextProps);
    return true;
  }),
  branch(
    ({ getRandomValue }) => getRandomValue % 2 === 0,
    renderComponent(props => {
      console.warn("left branch", props);
      return <Counter {...props} />;
    }),
    renderComponent(props => {
      console.warn("right branch", props);
      return <Counter {...props} />;
    })
  )
)(App);

feel free to check out this PR and use it with  yarn link and yarn link incompose on your project. would be glad to get some feedback from you.
NOTE: i've also switched the implementation of withLifecycle and shouldUpdate to use the hook api from inferno. not sure since when these are available but i've tested my code with inferno 7.1.13.

v5.0.1 shipped 🎉
https://www.npmjs.com/package/incompose
thanks again for your help @ioi0 👍