DPU-TRD Kernel image boot failure (Vitis flow)

Dear community,
Hello I'm currently working on building a kernel image following DPU-TRD Vitis flow: https://github.com/Xilinx/Vitis-AI/blob/1.3.1/dsa/DPU-TRD/prj/Vitis/README.md with zcu106 board, Vivado 2020.2
I modified some parameters for zcu106 board as it has less BRAMs and I had to build the required files such as .xsa, .xpfm from the scratch as there is no pre-built ones for zcu106 board. (Here is what I followed: https://www.xilinx.com/html_docs/xilinx2019_2/vitis_doc/Chunk1468064742.html#hog1570652702356 for building images and xpfm but It doesn't seem this is the reason)
As you can see in the log, everything seems fine until building the kernel image but when I flash the image (sd_card.img) using balenaEtcher and tried to boot on gtkterm, nothing shows up.

I've attached the full log. It is a bit more confusing because there is no any error message and it is still not booting.
It would be really appreciated if anyone can give me some advice on this error.
Thank you.
Best regards,
Joon
joon@joon-X299X-DESIGNARE-10G:~/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis$ export EDGE_COMMON_SW=/home/joon/dpu_prj/ttrl3/pfm3/xilinx-zynqmp-common-v2020.2
joon@joon-X299X-DESIGNARE-10G:~/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis$ export SDX_PLATFORM=/home/joon/dpu_prj/ttrl3/pfm3/wksp3/zcu106_B512_3/export/zcu106_B512_3/zcu106_B512_3.xpfm
joon@joon-X299X-DESIGNARE-10G:~/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis$ make KERNEL=DPU_SM DEVICE=zcu106
/home/joon/Xilinx/Vivado/2020.2/bin/vivado -mode batch -source /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/scripts/gen_dpu_xo.tcl -notrace -tclargs binary_container_1/dpu.xo DPUCZDX8G hw zcu106
****** Vivado v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/scripts/gen_dpu_xo.tcl -notrace
binary_container_1/dpu.xo
INFO: [IP_Flow 19-5654] Module 'DPUCZDX8G' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_def.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/dpu_conf.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagesynthesis.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagebehavioralsimulation.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/joon/Xilinx/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_GP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP2' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_CONTROL' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'interrupt' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXI_GP0'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'ASSOCIATED_RESET' with value 'ap_rst_n_2'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_rst_n_2': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
WARNING: [IP_Flow 19-5661] Bus Interface 'ap_clk_2' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n_2': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n_2' is not *resetn - please double check the POLARITY setting.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagesynthesis (Synthesis)': "/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Synthesis file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation: src/dpu_conf.vh
/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagebehavioralsimulation (Simulation)': "/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Simulation file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation: src/dpu_conf.vh
/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Simulation'.
Resolution: Remove the file from the specified file group.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/joon/Xilinx/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
INFO: [Common 17-206] Exiting Vivado at Mon Aug 30 10:21:00 2021...
/home/joon/Xilinx/Vivado/2020.2/bin/vivado -mode batch -source /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/scripts/gen_sfm_xo.tcl -notrace -tclargs binary_container_1/softmax.xo sfm_xrt_top hw zcu106
****** Vivado v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/scripts/gen_sfm_xo.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/joon/Xilinx/Vivado/2020.2/data/ip'.
WARNING: [IP_Flow 19-2162] IP 'fp_div' is locked:

IP definition 'Floating-point (7.1)' for IP 'fp_div' (customized with software release 2021.1) has a different revision in the IP Catalog. * Current project part 'xc7vx485tffg1157-1' and the part 'xc7z020clg400-2' used to customize the IP 'fp_div' do not match.
WARNING: [IP_Flow 19-2162] IP 'fp_convert' is locked:
IP definition 'Floating-point (7.1)' for IP 'fp_convert' (customized with software release 2021.1) has a different revision in the IP Catalog. * Current project part 'xc7vx485tffg1157-1' and the part 'xc7z020clg400-2' used to customize the IP 'fp_convert' do not match.
WARNING: [IP_Flow 19-2162] IP 'fp_exp' is locked:
IP definition 'Floating-point (7.1)' for IP 'fp_exp' (customized with software release 2021.1) has a different revision in the IP Catalog. * Current project part 'xc7vx485tffg1157-1' and the part 'xc7z020clg400-2' used to customize the IP 'fp_exp' do not match.
WARNING: [IP_Flow 19-2162] IP 'fp_acc' is locked:
IP definition 'Floating-point (7.1)' for IP 'fp_acc' (customized with software release 2021.1) has a different revision in the IP Catalog. * Current project part 'xc7vx485tffg1157-1' and the part 'xc7z020clg400-2' used to customize the IP 'fp_acc' do not match.
WARNING: [IP_Flow 19-2162] IP 'fp_add' is locked:
IP definition 'Floating-point (7.1)' for IP 'fp_add' (customized with software release 2021.1) has a different revision in the IP Catalog. * Current project part 'xc7vx485tffg1157-1' and the part 'xc7z020clg400-2' used to customize the IP 'fp_add' do not match.
INFO: [IP_Flow 19-5654] Module 'sfm_xrt_top' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_control' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'interrupt' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXI'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/joon/Xilinx/Vivado/2020.2/data/ip'.
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
INFO: [Common 17-206] Exiting Vivado at Mon Aug 30 10:21:22 2021...
v++ -t hw --platform /home/joon/dpu_prj/ttrl3/pfm3/wksp3/zcu106_B512_3/export/zcu106_B512_3/zcu106_B512_3.xpfm --save-temps --config /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/config_file/prj_config_104_2dpu --xp param:compiler.userPostSysLinkOverlayTcl=/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/syslink/strip_interconnects.tcl -l --temp_dir binary_container_1 --log_dir binary_container_1/logs --remote_ip_cache binary_container_1/ip_cache -o "binary_container_1/dpu.xclbin" binary_container_1/dpu.xo binary_container_1/softmax.xo
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.', 'vivado.' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/home/joon/Xilinx/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
**** SW Build (by xbuild) on 2020-11-18-05:13:29
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/reports/link
Log files: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/logs/link
Running Dispatch Server on port:37095
INFO: [v++ 60-1548] Creating build summary session with primary output /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin.link_summary, at Mon Aug 30 10:21:44 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Mon Aug 30 10:21:44 2021
Running Rule Check Server on port:41183
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/reports/link/v++_link_dpu_guidance.html', at Mon Aug 30 10:21:45 2021
INFO: [v++ 60-895] Target platform: /home/joon/dpu_prj/ttrl3/pfm3/wksp3/zcu106_B512_3/export/zcu106_B512_3/zcu106_B512_3.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/home/joon/dpu_prj/ttrl3/pfm3/wksp3/zcu106_B512_3/export/zcu106_B512_3/hw/zcu106_B512_3.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423] Target device: zcu106_B512_3
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [10:21:46] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/dpu.xo --xo /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/softmax.xo -keep --config /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/syslinkConfig.ini --xpfm /home/joon/dpu_prj/ttrl3/pfm3/wksp3/zcu106_B512_3/export/zcu106_B512_3/zcu106_B512_3.xpfm --target hw --output_dir /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int --temp_dir /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Mon Aug 30 10:21:47 2021
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/dpu.xo
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/softmax.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [10:21:47] build_xd_ip_db started: /home/joon/Xilinx/Vitis/2020.2/bin/build_xd_ip_db -ip_search 0 -sds-pf /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/zcu106_B512_2.hpfm -clkid 0 -ip /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/iprepo/xilinx_com_RTLKernel_DPUCZDX8G_1_0,DPUCZDX8G -ip /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/iprepo/xilinx_com_RTLKernel_sfm_xrt_top_1_0,sfm_xrt_top -o /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [10:21:53] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1631.219 ; gain = 375.852 ; free physical = 24393 ; free virtual = 58863
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [10:21:53] cfgen started: /home/joon/Xilinx/Vitis/2020.2/bin/cfgen -nk DPUCZDX8G:2 -sp DPUCZDX8G_1.M_AXI_GP0:HPC -sp DPUCZDX8G_1.M_AXI_HP0:HPC -sp DPUCZDX8G_1.M_AXI_HP2:HPC -sp DPUCZDX8G_2.M_AXI_GP0:HPC -sp DPUCZDX8G_2.M_AXI_HP0:HPC -sp DPUCZDX8G_2.M_AXI_HP2:HPC -clock.id 1:DPUCZDX8G_1.aclk -clock.id 1:DPUCZDX8G_1.ap_clk_2 -clock.id 2:DPUCZDX8G_2.aclk -clock.id 2:DPUCZDX8G_2.ap_clk_2 -dmclkid 0 -r /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: DPUCZDX8G, num: 2 {DPUCZDX8G_1 DPUCZDX8G_2}
INFO: [CFGEN 83-0] kernel: sfm_xrt_top, num: 1 {sfm_xrt_top_1}
INFO: [CFGEN 83-0] Port Specs:
INFO: [CFGEN 83-0] kernel: DPUCZDX8G_1, k_port: M_AXI_GP0, sptag: HPC
INFO: [CFGEN 83-0] kernel: DPUCZDX8G_1, k_port: M_AXI_HP0, sptag: HPC
INFO: [CFGEN 83-0] kernel: DPUCZDX8G_1, k_port: M_AXI_HP2, sptag: HPC
INFO: [CFGEN 83-0] kernel: DPUCZDX8G_2, k_port: M_AXI_GP0, sptag: HPC
INFO: [CFGEN 83-0] kernel: DPUCZDX8G_2, k_port: M_AXI_HP0, sptag: HPC
INFO: [CFGEN 83-0] kernel: DPUCZDX8G_2, k_port: M_AXI_HP2, sptag: HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_instr_addr to HPC for directive DPUCZDX8G_1.M_AXI_GP0:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_prof_addr to HPC for directive DPUCZDX8G_1.M_AXI_GP0:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base0_addr to HPC for directive DPUCZDX8G_1.M_AXI_HP0:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base1_addr to HPC for directive DPUCZDX8G_1.M_AXI_HP0:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base2_addr to HPC for directive DPUCZDX8G_1.M_AXI_HP0:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base3_addr to HPC for directive DPUCZDX8G_1.M_AXI_HP0:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base4_addr to HPC for directive DPUCZDX8G_1.M_AXI_HP2:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base5_addr to HPC for directive DPUCZDX8G_1.M_AXI_HP2:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base6_addr to HPC for directive DPUCZDX8G_1.M_AXI_HP2:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base7_addr to HPC for directive DPUCZDX8G_1.M_AXI_HP2:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_instr_addr to HPC for directive DPUCZDX8G_2.M_AXI_GP0:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_prof_addr to HPC for directive DPUCZDX8G_2.M_AXI_GP0:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base0_addr to HPC for directive DPUCZDX8G_2.M_AXI_HP0:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base1_addr to HPC for directive DPUCZDX8G_2.M_AXI_HP0:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base2_addr to HPC for directive DPUCZDX8G_2.M_AXI_HP0:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base3_addr to HPC for directive DPUCZDX8G_2.M_AXI_HP0:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base4_addr to HPC for directive DPUCZDX8G_2.M_AXI_HP2:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base5_addr to HPC for directive DPUCZDX8G_2.M_AXI_HP2:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base6_addr to HPC for directive DPUCZDX8G_2.M_AXI_HP2:HPC
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base7_addr to HPC for directive DPUCZDX8G_2.M_AXI_HP2:HPC
INFO: [CFGEN 83-2226] Inferring mapping for argument sfm_xrt_top_1.sm_src_addr to HPC
INFO: [CFGEN 83-2226] Inferring mapping for argument sfm_xrt_top_1.sm_dst_addr to HPC
INFO: [SYSTEM_LINK 82-37] [10:21:54] cfgen finished successfully
Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:01 . Memory (MB): peak = 1631.219 ; gain = 0.000 ; free physical = 24391 ; free virtual = 58863
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [10:21:54] cf2bd started: /home/joon/Xilinx/Vitis/2020.2/bin/cf2bd --linux --trace_buffer 1024 --input_file /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.xsd --temp_dir /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link --output_dir /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.xsd
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [10:21:56] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1631.219 ; gain = 0.000 ; free physical = 24370 ; free virtual = 58856
INFO: [v++ 60-1441] [10:21:56] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1587.078 ; gain = 0.000 ; free physical = 24405 ; free virtual = 58893
INFO: [v++ 60-1443] [10:21:56] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/sdsl.dat -rtd /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/cf2sw.rtd -nofilter /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/cf2sw_full.rtd -xclbin /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/xclbin_orig.xml -o /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [10:21:58] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1587.078 ; gain = 0.000 ; free physical = 24342 ; free virtual = 58856
INFO: [v++ 60-1443] [10:21:58] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram
INFO: [v++ 60-1454] Run Directory: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [10:21:59] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.85 . Memory (MB): peak = 1587.078 ; gain = 0.000 ; free physical = 24290 ; free virtual = 58807
INFO: [v++ 60-1443] [10:21:59] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /home/joon/dpu_prj/ttrl3/pfm3/wksp3/zcu106_B512_3/export/zcu106_B512_3/zcu106_B512_3.xpfm --remote_ip_cache /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/ip_cache -s --output_dir /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int --log_dir /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/logs/link --report_dir /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/reports/link --config /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/vplConfig.ini -k /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link --no-info --iprepo /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/xo/ip_repo/xilinx_com_RTLKernel_sfm_xrt_top_1_0 --iprepo /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/xo/ip_repo/xilinx_com_RTLKernel_DPUCZDX8G_1_0 --messageDb /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/run_link/vpl.pb /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
****** vpl v2020.2 (64-bit)
**** SW Build (by xbuild) on 2020-11-18-05:13:29
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
INFO: [VPL 60-839] Read in kernel information from file '/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/kernel_info.dat'.
INFO: [VPL 60-423] Target device: zcu106_B512_3
INFO: [VPL 60-1032] Extracting hardware platform to /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/vivado/vpl/.local/hw_platform
WARNING: /home/joon/Xilinx/Vitis/2020.2/tps/lnx64/jre9.0.4 does not exist.
[10:22:09] Run vpl: Step create_project: Started
Creating Vivado project.
[10:22:15] Run vpl: Step create_project: Completed
[10:22:15] Run vpl: Step create_bd: Started
[10:22:30] Run vpl: Step create_bd: Completed
[10:22:30] Run vpl: Step update_bd: Started
[10:22:30] Run vpl: Step update_bd: Completed
[10:22:30] Run vpl: Step generate_target: Started
[10:23:10] Run vpl: Step generate_target: Completed
[10:23:10] Run vpl: Step config_hw_runs: Started
[10:23:13] Run vpl: Step config_hw_runs: Completed
[10:23:13] Run vpl: Step synth: Started
[10:23:44] Block-level synthesis in progress, 0 of 33 jobs complete, 8 jobs running.
[10:24:14] Block-level synthesis in progress, 2 of 33 jobs complete, 6 jobs running.
[10:24:44] Block-level synthesis in progress, 7 of 33 jobs complete, 6 jobs running.
[10:25:14] Block-level synthesis in progress, 7 of 33 jobs complete, 8 jobs running.
[10:25:44] Block-level synthesis in progress, 8 of 33 jobs complete, 7 jobs running.
[10:26:15] Block-level synthesis in progress, 11 of 33 jobs complete, 5 jobs running.
[10:26:45] Block-level synthesis in progress, 11 of 33 jobs complete, 8 jobs running.
[10:27:15] Block-level synthesis in progress, 12 of 33 jobs complete, 7 jobs running.
[10:27:45] Block-level synthesis in progress, 15 of 33 jobs complete, 5 jobs running.
[10:28:15] Block-level synthesis in progress, 17 of 33 jobs complete, 7 jobs running.
[10:28:45] Block-level synthesis in progress, 17 of 33 jobs complete, 8 jobs running.
[10:29:15] Block-level synthesis in progress, 21 of 33 jobs complete, 5 jobs running.
[10:29:46] Block-level synthesis in progress, 25 of 33 jobs complete, 5 jobs running.
[10:30:16] Block-level synthesis in progress, 28 of 33 jobs complete, 5 jobs running.
[10:30:46] Block-level synthesis in progress, 28 of 33 jobs complete, 5 jobs running.
[10:31:16] Block-level synthesis in progress, 32 of 33 jobs complete, 1 job running.
[10:31:46] Top-level synthesis in progress.
[10:32:16] Top-level synthesis in progress.
[10:32:40] Run vpl: Step synth: Completed
[10:32:40] Run vpl: Step impl: Started
[10:35:42] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 13m 42s
[10:35:42] Starting logic optimization..
[10:35:42] Phase 1 Retarget
[10:36:13] Phase 2 Constant propagation
[10:36:13] Phase 3 BUFG optimization
[10:36:13] Phase 4 Shift Register Optimization
[10:36:13] Phase 5 Sweep
[10:36:13] Phase 6 Constant propagation
[10:36:13] Phase 7 Sweep
[10:36:13] Phase 8 Remap
[10:36:43] Phase 9 Post Processing Netlist
[10:37:13] Finished 3rd of 6 tasks (FPGA logic optimization).  Elapsed time: 00h 12m 35s
[10:49:48] Starting logic routing..
[10:50:18] Phase 1 Build RT Design
[10:50:18] Phase 2 Router Initialization
[10:50:18] Phase 2.1 Fix Topology Constraints
[10:50:18] Phase 2.2 Pre Route Cleanup
[10:50:49] Phase 2.3 Global Clock Net Routing
[10:50:49] Phase 2.4 Update Timing
[10:51:49] Phase 2.5 Update Timing for Bus Skew
[10:51:49] Phase 2.5.1 Update Timing
[10:52:19] Phase 3 Initial Routing
[10:52:19] Phase 3.1 Global Routing
[10:52:49] Phase 4 Rip-up And Reroute
[10:52:49] Phase 4.1 Global Iteration 0
[10:58:52] Phase 4.2 Global Iteration 1
[10:59:22] Phase 5 Delay and Skew Optimization
[10:59:22] Phase 5.1 TNS Cleanup
[10:59:22] Phase 5.1.1 Delay CleanUp
[10:59:22] Phase <IP_ADDRESS> Update Timing
[10:59:52] Phase 5.2 Clock Skew Optimization
[10:59:52] Phase 6 Post Hold Fix
[10:59:52] Phase 6.1 Hold Fix Iter
[10:59:52] Phase 6.1.1 Update Timing
[10:59:52] Phase 7 Route finalize
[10:59:52] Phase 8 Verifying routed nets
[11:00:23] Phase 9 Depositing Routes
[11:00:23] Phase 10 Route finalize
[11:00:23] Phase 11 Post Router Timing
[11:00:53] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 11m 04s
[11:00:53] Starting bitstream generation..
Starting optional post-route physical design optimization.
Finished optional post-route physical design optimization.
[11:03:54] Creating bitmap...
[11:04:37] Run vpl: Step impl: Completed
[11:04:38] Writing bitstream ./top_wrapper.bit...
[11:04:38] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 03m 44s
[11:04:38] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [11:04:38] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:18 ; elapsed = 00:42:39 . Memory (MB): peak = 1587.078 ; gain = 0.000 ; free physical = 24033 ; free virtual = 57257
INFO: [v++ 60-1443] [11:04:38] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/address_map.xml -sdsl /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/sdsl.dat -xclbin /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/xclbin_orig.xml -rtd /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.rtd -o /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.xml
INFO: [v++ 60-1652] Cf2sw returned exit code: 0
INFO: [v++ 60-2311] HPISystemDiagram::writeSystemDiagramAfterRunningVivado, rtdInputFilePath: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.rtd
INFO: [v++ 60-2312] HPISystemDiagram::writeSystemDiagramAfterRunningVivado, systemDiagramOutputFilePath: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json
INFO: [v++ 60-1618] Launching
INFO: [v++ 60-1441] [11:04:39] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1587.078 ; gain = 0.000 ; free physical = 24035 ; free virtual = 57276
INFO: [v++ 60-1443] [11:04:39] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/system.bit --force --target hw --key-value SYS:dfx_enable:false --add-section :JSON:/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu_xml.rtd --add-section BUILD_METADATA:JSON:/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu_build.rtd --add-section EMBEDDED_METADATA:RAW:/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.xml --add-section SYSTEM_METADATA:RAW:/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:xilinx_board_name_0_0 --output /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin
INFO: [v++ 60-1454] Run Directory: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
XRT Build Version: 2.8.0 ()
Build Date: 2021-08-20 11:33:03
Hash ID:
Creating a default 'in-memory' xclbin image.
Section: 'BITSTREAM'(0) was successfully added.
Size : 13643326 bytes
Format : RAW
File : '/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/system.bit'
Section: 'MEM_TOPOLOGY'(6) was successfully added.
Format : JSON
File : 'mem_topology'
Section: 'IP_LAYOUT'(8) was successfully added.
Format : JSON
File : 'ip_layout'
Section: 'CONNECTIVITY'(7) was successfully added.
Format : JSON
File : 'connectivity'
WARNING: Skipping CLOCK_FREQ_TOPOLOGY section for count size is zero.
WARNING: Section 'CLOCK_FREQ_TOPOLOGY' content is empty. No data in the given JSON file.
Section: 'CLOCK_FREQ_TOPOLOGY'(11) was empty. No action taken.
Format : JSON
File : '/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu_xml.rtd'
Section: 'BUILD_METADATA'(14) was successfully added.
Size : 6025 bytes
Format : JSON
File : '/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu_build.rtd'
Section: 'EMBEDDED_METADATA'(2) was successfully added.
Size : 7214 bytes
Format : RAW
File : '/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.xml'
Section: 'SYSTEM_METADATA'(22) was successfully added.
Size : 20035 bytes
Format : RAW
File : '/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json'
Successfully wrote (13691356 bytes) to the output file: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [11:04:40] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1587.078 ; gain = 0.000 ; free physical = 24021 ; free virtual = 57276
INFO: [v++ 60-1443] [11:04:40] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --force --info /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin.info --input /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin
INFO: [v++ 60-1454] Run Directory: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [11:04:40] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.29 . Memory (MB): peak = 1587.078 ; gain = 0.000 ; free physical = 24021 ; free virtual = 57278
INFO: [v++ 60-1443] [11:04:40] Run run_link: Step generate_sc_driver: Started
INFO: [v++ 60-1453] Command Line:
INFO: [v++ 60-1454] Run Directory: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [11:04:40] Run run_link: Step generate_sc_driver: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1587.078 ; gain = 0.000 ; free physical = 24021 ; free virtual = 57278
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/reports/link/system_estimate_dpu.xtxt
INFO: [v++ 60-2397] Platform default or user specified output type sd_card detected but is not a supported output for v++ --link. Use the v++ --package option instead to create SD card output.
INFO: [v++ 60-586] Created binary_container_1/dpu.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
Guidance: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/reports/link/v++_link_dpu_guidance.html
Timing Report: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/reports/link/imp/impl_1_top_wrapper_timing_summary_routed.rpt
Vivado Log: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/logs/link/vivado.log
Steps Log File: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/logs/link/link.steps.log
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command.
vitis_analyzer /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin.link_summary
INFO: [v++ 60-791] Total elapsed time: 0h 43m 5s
INFO: [v++ 60-1653] Closing dispatch client.
v++ -t hw --platform /home/joon/dpu_prj/ttrl3/pfm3/wksp3/zcu106_B512_3/export/zcu106_B512_3/zcu106_B512_3.xpfm -p binary_container_1/dpu.xclbin -o dpu.xclbin --package.out_dir binary_container_1 --package.rootfs /home/joon/dpu_prj/ttrl3/pfm3/xilinx-zynqmp-common-v2020.2/rootfs.ext4 --package.sd_file /home/joon/dpu_prj/ttrl3/pfm3/xilinx-zynqmp-common-v2020.2/Image
Option Map File Used: '/home/joon/Xilinx/Vitis/2020.2/data/vitis/vpp/optMap.xml'
****** v++ v2020.2 (64-bit)
**** SW Build (by xbuild) on 2020-11-18-05:13:29
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ package can be found at:
Reports: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/_x/reports/package
Log files: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/_x/logs/package
Running Dispatch Server on port:36573
INFO: [v++ 60-1548] Creating build summary session with primary output /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/dpu.xclbin.package_summary, at Mon Aug 30 11:04:51 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Mon Aug 30 11:04:52 2021
Running Rule Check Server on port:35815
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/_x/reports/package/v++_package_dpu_guidance.html', at Mon Aug 30 11:04:52 2021
INFO: [v++ 60-895] Target platform: /home/joon/dpu_prj/ttrl3/pfm3/wksp3/zcu106_B512_3/export/zcu106_B512_3/zcu106_B512_3.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/home/joon/dpu_prj/ttrl3/pfm3/wksp3/zcu106_B512_3/export/zcu106_B512_3/hw/zcu106_B512_3.xsa'
INFO: [v++ 60-2256] Packaging for hardware
Section: 'SYSTEM_METADATA'(22) was successfully written.
Format: RAW
File : '/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/_x/package/extractedSystemDiagram.json'
Section: 'BITSTREAM'(0) was successfully written.
Format: RAW
File : '/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/_x/package/system.bit'
WARNING: [v++ 82-1147] Kernel image is not specified for linux domain
INFO: [v++ 82-1025] generating bootimage
****** Xilinx Bootgen v2020.2
**** Build date : Nov 18 2020-09:50:31
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
[WARNING]: [fsbl_config] a53_x64 | a53_x32 | r5_single | r5_dual is no more supported. Use 'destination_cpu' attribute for bootloader partition
[INFO] : Bootimage generated successfully
INFO: [v++ 82-1011] creating sd_card directory
INFO: [v++ 82-3558] mkfsimage command run: /home/joon/Xilinx/Vitis/2020.2/scripts/vitis/util/mkfsImage.sh -s /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/sd_card/ -o /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/binary_container_1/sd_card.img -e /home/joon/dpu_prj/ttrl3/pfm3/xilinx-zynqmp-common-v2020.2/rootfs.ext4
FATSIZE:1024
fat_start:63
fat_end:2096639
fat_sector:2096577
ext4_start:0
ext4_sector:4833104
EXT4SIZE:2560
TOTALSIZE:3584
dummy_ext4_sector:409776
sd_card_fat_start:2048
sd_card_ext4_start:2000896
dummy_ext4_start:6834000
2096577+0 records in
2096577+0 records out
1073447424 bytes (1.1 GB, 1.0 GiB) copied, 2.28127 s, 471 MB/s
4833104+0 records in
4833104+0 records out
2474549248 bytes (2.5 GB, 2.3 GiB) copied, 5.22234 s, 474 MB/s
409776+0 records in
409776+0 records out
209805312 bytes (210 MB, 200 MiB) copied, 0.404818 s, 518 MB/s
Section: 'SYSTEM_METADATA'(22) was successfully added.
Size : 20071 bytes
Format : RAW
File : '/home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/x/package/packagedSystemDiagram.json'
Successfully wrote (13691388 bytes) to the output file: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/x/package/upsert.xclbin
INFO: [v++ 60-2460] Successfully copied a temporary xclbin to the output xclbin: /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/dpu.xclbin
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command.
vitis_analyzer /home/joon/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis/dpu.xclbin.package_summary
INFO: [v++ 60-791] Total elapsed time: 0h 14m 28s
INFO: [v++ 60-1653] Closing dispatch client.
cp ./binary/link/vivado/vpl/prj/prj/sources_1/bd//hw_handoff/.hwh ./binary/sd_card
cp ./binary_/link/vivado/vpl/prj/prj.gen/sources_1/bd//ip/DPUCZDX8G_1_0/arch.json ./binary*/sd_card
joon@joon-X299X-DESIGNARE-10G:~/dpu_prj/ttrl3/pfm3/DPU-TRD/prj/Vitis$

Please let me know if any log file required

Hi @likecaulfield
Could you boot up successfully with the SD card image without integrating the DPU?

Hi @qianglin-xlnx
I tried to boot with these three files but I failed.
BOOT.BIN, boot.scr, image.ub  (from ~images/linux)
I copied it into sd card and tried to boot with gtkterm but still nothing shows up.
Is it to do with software image build then?
Thank you.

*update2
Hi @qianglin-xlnx
I've found out that I might have made a mistake.
I built xsa file with DPU on Vivado and did integrate dpu on Vitis again.
Could it be the reason? I will try with no dpu integration on vivado.
Thank you.


Increase speed load according to Google page speed insights

https://developers.google.com/speed/pagespeed/insights/?url=Codeburrow.com&tab=mobile
Prio:Blocker
Status:In-Progress

Current google page speed ranking.

Closed by #24.


Remove: Termius.Termius version 7.54.2

The installer file has been updated to a newer version
Checklist for Pull Requests

[x] Have you signed the Contributor License Agreement?
[ ] Is there a linked Issue?

Manifests

[x] Have you checked that there aren't other open pull requests for the same manifest update/change?
[x] This PR only modifies one (1) manifest
[x] Have you validated your manifest locally with winget validate --manifest <path>?
[ ] Have you tested your manifest locally with winget install --manifest <path>?
[ ] Does your manifest conform to the 1.6 schema?

Note: <path> is the name of the directory containing the manifest you're submitting.

Microsoft Reviewers: Open in CodeFlow

URL: https://autoupdate.termius.com/windows/Termius.exe
Status Code: 200
(Automated message - build 872)


Support chubby75 board

Hi,
would it be possible to support https://github.com/q3k/chubby75 ?
I can try if you guide me a little bit. (I will also try if you won't)

my first try:
https://github.com/danielkucera/HDMI2USB-litex-firmware/commit/00ed664c7bf683f86777fcd526bf08b3a90b4694
it builds but I don't know how to continue. I can write top.bin to SPI flash but there is no uart defined. How do I do get some "shell" ?

@danielkucera If you know the net configuration works, you could try tftp or telnet?

I created a WIP pull request at https://github.com/timvideos/HDMI2USB-litex-firmware/pull/473 so we can see the progress.


fix not show error when using --lxc-conf without lxc driver

Signed-off-by: Ma Shimiao<EMAIL_ADDRESS>When use --lx-conf without lxc driver, the result will looks like:
$ docker run -d --name pctest --lxc-conf="lxc.network.type=veth" --lxc-conf="lxc.network.link=docker0" --lxc-conf="lxc.network.flags=up" ubuntu:14.04
FATA[0000] Error response from daemon: Could not use --lxc-conf with execdriver: native-0.2

Your new commit isn't signed--it's better to just "git commit --amend" as it does not to be a separate commit.  Please squash them to one, and make sure the one is signed.  Thanks!

You can also squash commits into one with git rebase -i upstream/master

Thanks, fixed.

LGTM

LGTM


Support for legacy UTxO witness in Jörmungandr

Issue Number

#779
Overview

[x] I have extended mkStdTx so that it would properly handle transactions coming from a RndKey and construct legacy-utxo witnesses for it.

Comments

Jörmungandr doesn't implement creating legacy utxo witnesses from jcli ...
jcli/src/jcli_app/transaction/mk_witness.rs
            WitnessType::OldUTxO => {
                // TODO unimplemented!()
                let _secret_key: SecretKey<Ed25519Bip32> = self.secret()?;
                Err(Error::MakeWitnessLegacyUtxoUnsupported)?;
                unimplemented!()
            }

so I had to construct them by hand according to:

The format defined in chain-impl-mockchain#witnesses

The format from the source (double checking it matches the doc..) chain-impl-mockchain/src/transaction/witness.rs

It'd be nice to review our golden if / when the constructor for the witness type gets updated.

bors r+

bors r-

bors r+


Added logo

Not sure if you'll like this or not, but I simply couldn't resist ;-) Viewable here:

https://github.com/haskell-lisp/hackett/tree/add-logo

If approved, I can change the links for the images to what they'd be in master ...

This is brilliant :)

This is really cool! Do you happen to have an SVG version of the logo, or is it just a bitmap?

Just bitmap ... but I can do an SVG one :-)
Will do some poking around in available software; I don't have my linux machine anymore and the new mac doesn't run Inkscape; I'll update the ticket with progress later today.

Okay, got it sorted :-) SVG has been added; can delete the .png files if that's preferred!


Improve lookup/from_name docs on Modal objects

I don't think we explain the distinction between .lookup and .from_name anywhere in our docs.
We've had various conversations about how to avoid having this dichotomy (which is somewhat easier now that nearly all objects support lazy hydration) but in the meantime I think it's helpful to explain a little bit about the difference.
I don't think the explanation is super helpful because I'm not certain the average user will be able to reason from the explanation that we give to the practical implications for their code. Which is why it's generally preferable to just have One Way To Do It. But hopefully the examples help a little bit in terms of guiding usage.
I also took the opportunity to modernize + standardize some of the other doctstring copy and examples, along with Jonofication of the capitalization.

@prbot approve; just docs

👍
thanks for doing this!


go-flags doesn't work with go's flag package

package main

import (
    "flag"
    "log"
    "github.com/jessevdk/go-flags"
)

var f = flag.Bool("a", false, "yeyey")

type A struct {
    X string `long:"tf" description:"testflag" default:"def_val" env:"TF"`
}

func main() {
    flag.Parse()
    a := &A{}
    parser := flags.NewParser(a, flags.IgnoreUnknown|flags.HelpFlag|flags.PrintErrors)
    _, err := parser.Parse()
    if err != nil {
        log.Fatal(err)
    }
    println(*f)
    println((*a).X)
}

$ go run flagtest.go --tf bc
flag provided but not defined: -tf
Usage of /tmp/go-build245317497/b001/exe/flagtest:
  -a    yeyey
exit status 2

After commenting the line, flag.Parse():
$ go run flagtest.go --tf bc
false
bc

The use-case occurs when you import a package which is using go's flag package and my package uses go-flags. In that case, go-flags are shadowed by the go's flag library.
Was this a thought out decision while designing? Are there any ways to use both of them together?

I have run into this as well just now. As much as I enjoy the go-flags package, it's interfering with my use of glog, which is also very convenient.

This is not a use case that go-flags was designed for. The error that you're getting is from the flag package from what I can see. I don't think it make much sense to use multiple flags parsers at the same time. You could try passing the "rest" arguments returned from Parse from go-flags to the CommandLine.Parse from go flag and see if that works for you. Otherwise this is simply not a goal for go-flags to support.


Print in middleware component

In version 5.8.2 the PrometheusInstrumentatorMiddleware prints to stdout on every request, this should not be in the release:
https://github.com/trallnag/prometheus-fastapi-instrumentator/blob/master/prometheus_fastapi_instrumentator/middleware.py#L80
Workaround: Downgrade to 5.8.1

Hahahaha I was going crazy, looking for print statements in my own code, then in every involved library (uvicorn, starlette, fastapi, ...) 🤣

I went through all the code looking for this print...
Waiting for a fix 🙃

Hope this is fixed soon

Fixed in #157. Will be released soon(tm)


Change the direction of the arrows for "Faucet"

Change the direction of the arrows on the "deposit" and "withdraw" buttons
deposit - up arrow
withdraw - down arrow

checked

checked


Installation on Mac M1

Hello,
after successfully installing the required packages with "pip install ocatari" and  "pip install "gymnasium[atari, accept-rom-license]"" on my Mac M1, I wanted to try the demo code
from ocatari.core import OCAtari
import random

env = OCAtari("Pong", mode="ram", hud=True, render_mode="rgb_array")
observation, info = env.reset()
action = random.randint(env.nb_actions-1)
obs, reward, terminated, truncated, info = env.step(action)

however, I get the following error:
zsh: segmentation fault  /Users/aarist/miniforge3/envs/oc_atari/bin/python
Any ideas how I can resolve this?
Kind regards
Andi

Can you give us a bit more indication on where the segmentation fault is being raised ?
You can also try to clone the repository and do pip install -e . from inside the OC_Atari folder.

It happens during the import "from ocatari.core import OCAtari". When I run the program, I either receive "zsh: segmentation fault ..." or a "zsh: bus fault ...". There are no further error outputs.
I also set up the Dockerfile, but when I wanted to try the demo it raised the error "AttributeError: module 'cv2.dnn' has no attribute 'DictValue'". After trying to change the opencv version, I now get the following error:
root@f0cd617ee134:~/oc_atari# /bin/python /root/oc_atari/demo_oc_atari.py
/usr/local/lib/python3.8/dist-packages/gymnasium/envs/registration.py:521: UserWarning: WARN: Using the latest versioned environment Pong-v4 instead of the unversioned environment Pong.
logger.warn(
A.L.E: Arcade Learning Environment (version 0.8.1+53f58b7)
[Powered by Stella]
Undefined mode for information extraction


Allow RDP access similar to SSH/HTTPS access

Thanks for contributing to pcf-pipelines. To speed up the process of reviewing your pull request please provide us with:

A short explanation of the proposed change:
Enable RDP access to Windows stemcells via Opsman

An explanation of the use cases your change solves:
If you use the Pivotal Application Service for Windows tile (previously PCF Runtime for Windows) and limit access to your Ops Manager to certain IP addresses, you will not be able to RDP to the Windows stemcells. This PR follows the pattern for HTTPS/SSH access.

Expected result after the change:
After opening a ssh tunnel to the ops manager, you'll be able to open an RDP session to a windows stemcell.

Current result before the change:
Unable to RDP to Windows stemcells via Opsman

Links to any other associated PRs or issues:

[X ] I have viewed signed and have submitted the Contributor License Agreement

[X ] I have made this pull request to the master branch

[X ] I have run all the unit tests

Thanks for the suggest and PR we are revisiting how the iaas paving will work in future iterations and will take this requirement into consideration.


Poor datagram extension send performance

I noticed that the sending rate of datagram frames is much lower than that of stream frames.
Example measurement with streams:
$ qperf client --addr [::1]:18080 --receive-stream
{"qlog_format":"NDJSON","qlog_version":"draft-02","title":"quic-go qlog","code_version":"v0.33.0","trace":{"vantage_point":{"type":"client"},"common_fields":{"ODCID":"a7a4f894c0eb3547b4","group_id":"a7a4f894c0eb3547b4","reference_time":1680959374739.0117,"time_format":"relative"}}}
{"time":0.009531,"name":"transport:connection_started","data":{"ip_version":"ipv6","src_ip":"::","src_port":36664,"dst_ip":"::1","dst_port":18080,"src_cid":"(empty)","dst_cid":"a7a4f894c0eb3547b4"}}
{"time":2.909691,"name":"qperf:handshake_completed","data":{}}
{"time":3.156259,"name":"qperf:handshake_confirmed","data":{}}
{"time":3.194904,"name":"qperf:first_app_data_received","data":{}}
{"time":1003.043641,"name":"qperf:report","data":{"stream_mbps_received":1795.8972,"stream_bytes_received":225188568,"max_rtt":2.245394,"packets_lost":0,"period":1003.1245}}
{"time":2003.067291,"name":"qperf:report","data":{"stream_mbps_received":1830.302,"stream_bytes_received":228793158,"max_rtt":0.318308,"packets_lost":0,"period":1000.0236}}
{"time":3003.103221,"name":"qperf:report","data":{"stream_mbps_received":1851.251,"stream_bytes_received":231414678,"max_rtt":0.323288,"packets_lost":0,"period":1000.0359}}
{"time":4003.111423,"name":"qperf:report","data":{"stream_mbps_received":1771.6084,"stream_bytes_received":221452902,"max_rtt":0.360415,"packets_lost":0,"period":1000.0083}}
{"time":5003.120854,"name":"qperf:report","data":{"stream_mbps_received":1726.5168,"stream_bytes_received":215816634,"max_rtt":0.314119,"packets_lost":0,"period":1000.0094}}
{"time":6003.125988,"name":"qperf:report","data":{"stream_mbps_received":1813.5583,"stream_bytes_received":226695942,"max_rtt":0.449681,"packets_lost":0,"period":1000.005}}
{"time":7003.172815,"name":"qperf:report","data":{"stream_mbps_received":1794.6083,"stream_bytes_received":224336574,"max_rtt":0.344474,"packets_lost":0,"period":1000.04694}}
{"time":8003.190618,"name":"qperf:report","data":{"stream_mbps_received":1827.6912,"stream_bytes_received":228465468,"max_rtt":0.314881,"packets_lost":0,"period":1000.0179}}
{"time":9003.246401,"name":"qperf:report","data":{"stream_mbps_received":1836.0106,"stream_bytes_received":229514076,"max_rtt":0.989975,"packets_lost":0,"period":1000.0556}}
{"time":10003.279565,"name":"qperf:report","data":{"stream_mbps_received":1825.5658,"stream_bytes_received":228203316,"max_rtt":1.303156,"packets_lost":0,"period":1000.03326}}
{"time":10003.284284,"name":"qperf:total","data":{"stream_mbps_received":1807.2968,"stream_bytes_received":2259881316,"max_rtt":2.245394,"packets_lost":0,"period":10003.365}}
{"time":10003.305172,"name":"transport:connection_closed","data":{"owner":"local","application_code":0,"reason":"no error"}}

Example measurement with datagrams:
$ qperf client --addr [::1]:18080 --receive-datagram
{"qlog_format":"NDJSON","qlog_version":"draft-02","title":"quic-go qlog","code_version":"v0.33.0","trace":{"vantage_point":{"type":"client"},"common_fields":{"ODCID":"9e300937c45af3898daf61a0908e01b8db96","group_id":"9e300937c45af3898daf61a0908e01b8db96","reference_time":1680959355161.2058,"time_format":"relative"}}}
{"time":0.00856,"name":"transport:connection_started","data":{"ip_version":"ipv6","src_ip":"::","src_port":48185,"dst_ip":"::1","dst_port":18080,"src_cid":"(empty)","dst_cid":"9e300937c45af3898daf61a0908e01b8db96"}}
{"time":2.485886,"name":"qperf:handshake_completed","data":{}}
{"time":2.820795,"name":"qperf:first_app_data_received","data":{}}
{"time":3.490911,"name":"qperf:handshake_confirmed","data":{}}
{"time":1002.568919,"name":"qperf:report","data":{"datagram_mbps_received":882.97943,"datagram_bytes_received":110665044,"max_rtt":1.745657,"packets_lost":0,"period":1002.6511}}
{"time":2002.587988,"name":"qperf:report","data":{"datagram_mbps_received":911.00494,"datagram_bytes_received":113877792,"max_rtt":0.262073,"packets_lost":0,"period":1000.01904}}
{"time":3002.59966,"name":"qperf:report","data":{"datagram_mbps_received":904.002,"datagram_bytes_received":113001588,"max_rtt":0.22669,"packets_lost":0,"period":1000.0118}}
{"time":4002.610865,"name":"qperf:report","data":{"datagram_mbps_received":896.38965,"datagram_bytes_received":112049973,"max_rtt":0.196076,"packets_lost":0,"period":1000.0113}}
{"time":5002.665301,"name":"qperf:report","data":{"datagram_mbps_received":906.9607,"datagram_bytes_received":113376249,"max_rtt":0.192185,"packets_lost":0,"period":1000.0544}}
{"time":6002.71468,"name":"qperf:report","data":{"datagram_mbps_received":899.3048,"datagram_bytes_received":112418649,"max_rtt":0.565357,"packets_lost":0,"period":1000.0493}}
{"time":7002.767639,"name":"qperf:report","data":{"datagram_mbps_received":899.80896,"datagram_bytes_received":112482090,"max_rtt":0.171022,"packets_lost":0,"period":1000.05304}}
{"time":8002.79533,"name":"qperf:report","data":{"datagram_mbps_received":907.004,"datagram_bytes_received":113378643,"max_rtt":0.238366,"packets_lost":0,"period":1000.02765}}
{"time":9002.826728,"name":"qperf:report","data":{"datagram_mbps_received":919.2863,"datagram_bytes_received":114914394,"max_rtt":0.250257,"packets_lost":0,"period":1000.0314}}
{"time":10002.835764,"name":"qperf:report","data":{"datagram_mbps_received":896.7557,"datagram_bytes_received":112095459,"max_rtt":0.263642,"packets_lost":0,"period":1000.0089}}
{"time":10002.838008,"name":"qperf:total","data":{"datagram_mbps_received":902.34436,"datagram_bytes_received":1128259881,"max_rtt":1.745657,"packets_lost":0,"period":10002.921}}
{"time":10002.859898,"name":"transport:connection_closed","data":{"owner":"local","application_code":0,"reason":"no error"}}

I narrowed the problem down to the send queue of capacity one and the blocking until the datagram is dequeued, i.e.,
sendQueue: make(chan *wire.DatagramFrame, 1) and h.dequeued <- struct{}{} in datagram_queue.go.

Your analysis is correct. We haven't spent any effort optimizing the sending / receiving of datagrams yet.

@marten-seemann  I have tested that using a sync.pool like the current stream frames pool can make some improvement on both sending and receiving. I can make a pr if you don't think it's a bad idea.

Would like to do some work on this if I can be pointed in the right direction. For the send queue it seems like we just need to increase the channel size to something reasonable. There's a lot of locking in the receive path and I'm thinking perhaps rcvQueue and rcvMx could be replaced with a channel?

I'm also interested in this - it's not critical for my use case and I'm still trying to get some other things working, but good throughput is critical for me and in a perfect world it'd be slightly better to use datagrams as opposed to streams. @dongcarl have you been doing any work on it?

Is this performance issue fully fixed now?
It still reads as unfixed in the main README.

This issue is closed and won't be updated.

@marten-seemann you may want to update this page in the documentation
https://quic-go.net/docs/quic/datagrams/


fix: make typescript test example spec compliant

Proposed changes
See https://github.com/pulumi/examples/pull/608#discussion_r400767835

Unreleased product version (optional)

Related issues (optional)

@komalali thoughts? I know you are making some improvements in some areas for this

I haven't touched anything specific to this particular case, but the reasoning looks sound to me following the conversation at https://github.com/pulumi/examples/pull/608#discussion_r400767835
@mikhailshilkov was involved in the original convo so tagging him here, but looks good to me and thanks for the improvement @SimenB !


Upgrade to source_gen 0.5.0.

This change is

Previously, davidmorgan (David Morgan) wrote…
> #### Upgrade to source\_gen 0\.5\.0\.

Review status: 0 of 22 files reviewed at latest revision, all discussions resolved.

Comments from Reviewable


API Key

I would like to request an API key for the Washington DC team.

Keys will go out this weekend over BDPA Slack. If your chapter still hasn't gotten a key by Sunday, reply back here or DM me on Slack

Thanks
On Sat, Jun 5, 2021 at 6:19 AM, @.***> wrote:
Keys will go out this weekend over BDPA Slack. If your chapter still hasn't gotten a key by Sunday, reply back here or DM me on Slack
—
You are receiving this because you authored the thread.
Reply to this email directly, view it on GitHub, or unsubscribe.

@Awoolen Closing this for now. API keys are going out over Slack. Please request one through the official channel, thanks!


Support application memento for extensions

Does this issue occur when all extensions are disabled?: Yes

VS Code Version: 1.71-insider
OS Version: Windows 11

Steps to Reproduce:

Go to https://insiders.vscode.dev/github/microsoft/vscode
Open an existing file and make some edits without committing
Use Settings Profiles: Create...
Create a new empty profile
:bug: files disappear

Additionally, in the explorer the root folder has this decoration which usually indicates that a fs.stat on the root directory URI threw an error

If I remember correctly, you store these local changes in extension global storage directory and also use global memento to remember the manifest of these files? We only switch global memento when profile is switched and global storage is across profile (application scoped).
@bpasero This needs introducing application / profile scope to extension state.

@sandy081 to clarify, this means to expose new API to extensions applicationState: Memento that is valid across profiles?

Correct!! But before that, @joyceerhl I would like to understand why you are storing the state in global memento? Is not this is workspace information and has to be stored in workspace memento?

@sandy081 we store metadata in global storage which says which URIs contain working changes--the actual working copy is stored in the ext file storage location provided in the extension context. This is global in order to provide the Remote Repositories view which displays all repositories you have visited and whether they contain uncommitted changes, regardless of which repository you happen to be currently looking at.

We closed this issue because we don't plan to address it in the foreseeable future. If you disagree and feel that this issue is crucial: we are happy to listen and to reconsider.
If you wonder what we are up to, please see our roadmap and issue reporting guidelines.
Thanks for your understanding, and happy coding!


Documentation PDF 404's on flask site

This link:
http://flask.pocoo.org/docs/flask-docs.pdf
on this page:
http://flask.pocoo.org/
Generates a 404.

Duplicate of pocoo/metaflask#7 and all these.

When its get fixed? Flask users really need this.... :)


feat(Analysis/EGauge): new file

Define egauge, needed to define Fréchet derivative
for functions between topological vector spaces.

bors merge


[ MB-11281 ] Enable destination type to be displayed in Move history table

MB-11281 for this change
Setup to Run Your Code

💻 You will need to use two separate terminals to test this locally.
Terminal 1
Start the UI locally.
make client_run

Terminal 2
Start the Go server locally.
make server_run

Additional steps

Access the office app
Login as a service councilor
Modify a shipment for a move (Any move with a shipment should work, I used BT93XH most recently)
Make sure that you modify the Destination Type, which is located under the address in the Delivery Location section
Go to the Move History for that move
You should see an entry for the Updated Shipment with the Destination Type info

Verification Steps for Author
These are to be checked by the author.

[ ] Have the Jira acceptance criteria been met for this change?

Screenshots
Before:

After:

Messages

:book:
:link: MB-11281

  Generated by :no_entry_sign: dangerJS against 97a0028021bc4b8854eb21da5a83fc451935c17b


Handle IAC scans on CI after force pushing

Codecov Report
Attention: 13 lines in your changes are missing coverage. Please review.

Comparison is base (801194f) 91.93% compared to head (ca95d6f) 91.73%.

Files
Patch %
Lines

ggshield/core/git_hooks/ci/previous_commit.py
29.41%
12 Missing :warning:

ggshield/cmd/iac/scan/diff.py
0.00%
1 Missing :warning:

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Additional details and impacted files
@@                          Coverage Diff                           @@
##           pbes/fix-prepush-new-branch-github     #837      +/-   ##
======================================================================
- Coverage                               91.93%   91.73%   -0.20%
======================================================================
  Files                                     168      168
  Lines                                    6952     6968      +16
======================================================================
+ Hits                                     6391     6392       +1
- Misses                                    561      576      +15

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Performance improvement for measure bounding box

[x] Have you followed the guidelines in our Contributing document?
[x] Have you checked to ensure there aren't other open Pull Requests for the same update/change?
[x] Does your submission pass tests?

This should improve measureBoundingBox performance for cases when geometry is translated or scaled.
function is added to mat4 isOnlyTransformScale to help recognize such matrix.
The idea is to measure bounding box of the geometry without the transform, and then apply transform to the bounding box.

UG. This is disappointing. Having to test the transforms is definitely not ideal.
I was having the same question… especially about a transform that mirrors the geometry.

UG. This is disappointing. Having to test the transforms is definitely not ideal.

well, identity check is everywhere as well :) there is small performance overhead ofc. that would be significant if geometry would have under 10 points and if there would be thousands of them. Also caching makes hitting the measurement code less often.

I have a possible solution that could be used for any type of transform but would make a little bit wider bounding box.
If we could loosen the requirement for bounding box (at least form some operations) we could trade precision for speed

it does not have  be as tight as now
is only required to catch the geometry bounds approximately
is only required that geometry does not leak outside of the bounding box

The idea is such that we use the initial bounding box (before transforms) as an approximation for our geometry.
Then we have a cuboid that approximates our underlying complex geometry and calculate any future boundingBox from that cuboid (constant time, regardless of geometry complexity).
here is an example of what I had in mind and how different is precision bounding box (red) and fast bounding box green
http://3d.hrg.hr/jscad/three/threejscad.html?uri=#model.measureBoundingBox.js

blue cylinder and red bounding box
blue cylinder and red bounding box, both rotated
precision bounding box based on the cylinder points
fast bounding box based on approximation
visualisation of different size calculated for precision bb and fast bb

In case a precise and tight box is also needed, we could have 2 versions (one for speed and one for precision)

I believe the requirement is for precision as designs often use the bounding box to calculate offsets. I often use the bounding box to calculate dimensions (H/W/D), and position pieces for boolean operations.
A non-precision version might be useful for internals, such as determining if two shapes overlap. This may be the only use… I’ll post back if there are additional uses cases.

@z3dev I have found an additional path to improve performance of measureBoundingBox.
I we allow internall for geometry creation functions to calculate bounding box and provide it to measureBoundingBox's cache we can allow fast calculation of bounding box for cases where it can be calculated form geometry parameters.
I have added an example implementation for ellipsoid (when default axes are used)
  const geom = geom3.create(polygons)

  // if default axes are used, bounding box is trivial to calculate
  if (noAxes) {
    // we just use the radiuses to easily calculate the corners for bounding box
    // and we also account for when center points are != 0
    const boundingBox = [
      radius.map((p,i) => -p + center[i] ),
      radius.map((p,i) =>  p + center[i] )
    ]
    measureBoundingBox.setCache(geom, boundingBox)
  }

  return geom

and this could be done for number of geometries, also would allow such performance shortcut for external libraries too.
Even when there is no cool trick to calculate boundingBox, I think it could be beneficial to calculate it right away as geometry points are added in some cases, as it should be faster as it can avoid a second pass through all the points later.

@z3dev please review, or comment if further improvements are needed here. Although this PR did not deliver performance for all transforms, I think it is still worth merging.
I would like to finish this one, and then look to make this alternative less precise(but fast) bounding box in separate PR.
That one could still be used by some operations like booleans the check overlap, but is not suitable for align.
The bounding box with less precission still guarantees the geometry is not outside of it, and should bring some more performance gains.

reverted

my first attempt at proper merge :)


Allow React 16 as peerDependency for 4.x

This is currently causing warnings in our React Native builds at Facebook.
Could you please merge this and release a bump?
I could do this myself but I haven't released in a while and don't want to screw up 😛

Yep, no problem.

Oh wait, this is for 4.0. Did those teams run into problems moving to 5.0? I know that might be a bigger ask, but BC should be maintained despite the major bump.

Pushed as 4.4.7

I don't think we're using 5.x anywhere yet, will raise issues if we find problems.


Failed to watch *v1beta1.FlowSchema

Environmental Info:
K3s Version: HA installation 1.19.5+k3s2
k3s version v1.19.5+k3s2
Cluster Configuration:
2xMaster
3xWorkers
Describe the bug:
When upgrading to client-go v0.20.0, an error message appears in the logs Failed to watch *v1beta1.FlowSchema
Full error from the logs

E0114 10:54:43.953522       1 reflector.go:138] pkg/mod/k8s.io/client-go@v0.20.0/tools/cache/reflector.go:167: Failed to watch *v1beta1.FlowSchema: failed to list *v1beta1.FlowSchema: flowschemas.flowcontrol.apiserver.k8s.io is forbidden: User "system:serviceaccount:cert-manager:cert-manager-webhook-duckdns" cannot list resource "flowschemas" in API group "flowcontrol.apiserver.k8s.io" at the cluster scope

Issue fixed in latest release v1.1 with commit e69150489d488c9ecbe6a795b4314b5a234f88e8.
Tested with kind node versions 1.19.4 and 1.20.0 and k3s v1.19.5+k3s2

Issue fixed in latest release v1.1 with commit e69150489d488c9ecbe6a795b4314b5a234f88e8.
Tested with kind node versions 1.19.4 and 1.20.0 and k3s v1.19.5+k3s2

Issue seems to have re-appeared but is not as problematic as before (the pod starts and seems to run without any troubles)
Error from the log
E0324 22:55:06.814142 1 reflector.go:138] pkg/mod/k8s.io/client-go@v0.20.2/tools/cache/reflector.go:167: Failed to watch *v1beta1.PriorityLevelConfiguration: failed to list *v1beta1.PriorityLevelConfiguration: prioritylevelconfigurations.flowcontrol.apiserver.k8s.io is forbidden: User "system:serviceaccount:cert-manager:cert-manager-webhook-duckdns" cannot list resource "prioritylevelconfigurations" in API group "flowcontrol.apiserver.k8s.io" at the cluster scope

E0324 22:55:06.750019 1 reflector.go:138] pkg/mod/k8s.io/client-go@v0.20.2/tools/cache/reflector.go:167: Failed to watch *v1beta1.FlowSchema: failed to list *v1beta1.FlowSchema: flowschemas.flowcontrol.apiserver.k8s.io is forbidden: User "system:serviceaccount:cert-manager:cert-manager-webhook-duckdns" cannot list resource "flowschemas" in API group "flowcontrol.apiserver.k8s.io" at the cluster scope

PR #5 seems to not still fix this


Do not call React hooks inside other hooks or conditions

My app is complaining in the console about a hooks error:

But I went to investigate and my components are following the rules for hooks described in the React documentation. I looked deeper and I discovered that the errors are in your package, specifically in these lines:
https://github.com/troch/reinspect/blob/4f3a562ae0d6bf6ee9198362b21d224a304315d5/src/useReducer.ts#L71-L74
https://github.com/troch/reinspect/blob/4f3a562ae0d6bf6ee9198362b21d224a304315d5/src/useState.ts#L12-L15
https://github.com/troch/reinspect/blob/e682221e0336df10a51ff9c7e1c24c7054c3b1fb/src/useState.ts#L18-L20
https://github.com/troch/reinspect/blob/e682221e0336df10a51ff9c7e1c24c7054c3b1fb/src/useReducer.ts#L77-L79
I tried to fix it for you but you're going to have to rewrite a part of the code.

Hello, should be fixed now with v1.0.0 (warning appeared in v16.8.0 of React).


Night Shift doesn't kick in

Night Shift doesn't kick in when using Discrete Only.
Plus, if Night Shift is active by any chance, it gets disabled by itself when screen is locked (and slept) and came back.

I'll try it on my computer.  This just may be behavior of how night shift works depending on which gpu is active though and not something I can fix.

Oh, I see. But it doesn't happen when I turn off automatic switching from
the Energy Saver menu.
Thanks for this app, by the way!
6 Nis 2020 Pzt 00:18 tarihinde Cody Schrank<EMAIL_ADDRESS>şunu
yazdı:

I'll try it on my computer. This just may be behavior of how night shift
works depending on which gpu is active though and not something I can fix.
—
You are receiving this because you authored the thread.
Reply to this email directly, view it on GitHub
https://github.com/CodySchrank/gSwitch/issues/48#issuecomment-609485075,
or unsubscribe
https://github.com/notifications/unsubscribe-auth/AFPRSCMPJNRK665F4EUKSS3RLDYR5ANCNFSM4MBM4SWQ
.

I just tried it myself multiple times and night shift stayed on when in discrete only when I locked my computer and when closed the display.
PS.  I personally use f.lux, it's a lot more customizable than night shift.  And I've never had a problem with gSwitch and f.lux


Import few property in netframework props for core

Fix https://github.com/microsoft/msbuild/issues/4782
By extracting these props
Tested locally with override files. TargetFrameworkSDKToolsDirectory is set

@rainersigwald how to trigger a test insertion? I named it /exp already

It seems your build failed:
https://dev.azure.com/devdiv/DevDiv/_build/results?buildId=3221285&view=results

@BenVillalobos looks like the magic for exp/ branches isn't quite there yet; I rescheduled the build with an updated IbcSourceBranchName=master here: https://devdiv.visualstudio.com/DevDiv/_build/results?buildId=3223318. When complete it should automatically insert; you can check for the insertion PR on the internal MSBuild/VS dashboard.


Restore minified core and sound libraries to resolve #1128 and #1131

Fixes #[1128] and #[1131]
Changes:
p5.min.js file restored, v1.4.0
p5.sound.min.js file restored, v1.0.1
Screenshots of the change:

Should be fixed now. Thanks.


New package: BoolExprs v0.1.0

Registering package: BoolExprs
Repository: https://github.com/bpr/BoolExprs.jl
Created by: @bpr
Version: v0.1.0
Commit: a150eb188a57dfb00784164f520cd2690dcb6f65
Reviewed by: @bpr
Reference: https://github.com/bpr/BoolExprs.jl/commit/a150eb188a57dfb00784164f520cd2690dcb6f65#commitcomment-53318691

@bpr please see the message above.  Once you fix the automerge issues you can register again the new revision without changing the version number and this pull request will be automatically updated.
[noblock]


Image Privacy

Hopefully it's good enough???

This can be improved over the last second hack job I did.


Python3.5 fix for next()

Python3.5 fix for next()
http://stackoverflow.com/questions/20484195/typeerror-range-object-does-not-support-item-assignment

Current coverage is 51.32%

Branch #308 has no coverage reports uploaded yet.

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Fixed on devel branch


Update to spring-boot 2.4.3 and other dependencies

Include migration of:

infinispan version to 11.0.9.Final
mongock version to 4.3.4

If this passes, I think it's OK to merge.


HOCS-5251: Remove actionDataUuid from Docs service

JIRA Link : https://collaboration.homeoffice.gov.uk/jira/browse/HOCS-5251

This needs the table column removing as well - along with removing the property from the DocumentData entity.

This could be done in a separate PR, release 1 to remove from the DTO, release 2 to remove from the table?

Yep agreed for the table but should still be part of the ticket. Removing from the entity in this case does need to be done here. That way we can avoid breaking changes on release.

can we coordinate merging this in too: https://github.com/UKHomeOffice/hocs-docs/pull/254  to avoid a double major version increment.


Javascript syntax highlighting breaks when using "" as key and value begins with "("

Steps to Reproduce:

Open new JS file
Paste the following code:

var a = {'\\': '('};

function function1() {
  console.log("hello".toUpperCase());
}

function function2() {
  console.log("hello".toUpperCase());
}

console.log("hello".toUpperCase());

Screenshot:

VS Code version: Code 1.36.1 (2213894ea0415ee8c85c5eea0d0ff81ecc191529, 2019-07-08T22:59:35.033Z)
OS version: Windows_NT x64 10.0.17763

Confirmed with the latest grammar from master


fix(Colors): add severity scale

@julesbarr Could you also extend the ColorTypes enum (https://github.com/securityscorecard/design-system/blob/alpha/src/theme/colors.enums.ts#L1)


Added new book: Neural Networks and Learning Machines (3rd edition)

What does this PR do?
Added a new book for Neural Networks and Machine Learning (Neural Networks and Learning Machines (3rd edition))
For resources
Haykin's 3rd edition covers neural networks, supervised learning, RBF networks, and regularization theory, offering a comprehensive and readable treatment.
Why is this valuable (or not)?
Simon Haykin's book on neural networks is valuable because it offers a comprehensive and up-to-date exploration of the subject. It covers classical supervised learning, kernel methods like RBF networks, and essential regularization theory. This thorough treatment makes it an excellent resource for both beginners and experienced practitioners in the field of machine learning, facilitating a deep understanding of neural networks and their applications.
How do we know it's really free?
It is freely available on this website under the Neural Networks course.
For book lists, is it a book? For course lists, is it a course? etc.
Book
Checklist:

[x] Read our contributing guidelines.
[x] Search for duplicates.
[x] Include author(s) and platform where appropriate.
[x] Put lists in alphabetical order, correct spacing.
[x] Add needed indications (PDF, access notes, under construction).
[x] Used an informative name for this pull request.

This appears not to be an authorized distribution. Please see docs/CONTRIBUTING.md guidelines.


operator [N] kong-gateway-operator (0.0.3)

Thanks submitting your Operator. Please check below list before you create your Pull Request.
New Submissions

[ ] Are you familiar with our contribution guidelines?
[ ] Have you packaged and deployed your Operator for Operator Framework?

[ ] Have you tested your Operator in all supported installation modes?

[x] Is your submission signed?
[x] Is operator icon set?

Your submission should not

[ ] Modify more than one operator
[ ] Modify an Operator you don't own
[ ] Rename an operator - please remove and add with a different name instead
[ ] Modify any files outside the above mentioned folders
[ ] Contain more than one commit. Please squash your commits.

Operator Description must contain (in order)

[ ] Description about the managed Application and where to find more information
[ ] Features and capabilities of your Operator and how to use it
[ ] Any manual steps about potential pre-requisites for using your Operator

Operator Metadata should contain

[x] Human readable name and 1-liner description about your Operator
[x] Valid category name1
[x] One of the pre-defined capability levels2
[ ] Links to the maintainer, source code and documentation
[x] Example templates for all Custom Resource Definitions intended to be used
[x] A quadratic logo

Remember that you can preview your CSV here.
--
1 If you feel your Operator does not fit any of the pre-defined categories, file an issue against this repo and explain your need
2 For more information see here

/merge possible

@pmalek please check your CSV file against https://operatorhub.io/preview. System is unable to read it.

How so? I was able to copy-paste https://raw.githubusercontent.com/k8s-operatorhub/community-operators/1afbd5f468a7a174146384780e52e978ca1c14e4/operators/kong-gateway-operator/0.0.3/manifests/kong-gateway-operator.clusterserviceversion.yaml into and it renders it no problem.

/merge possible

/merge possible

/merge possible

/merge possible


USB webcam glitches , Pi camera does not

Hello.
I am experimenting with v4l2rtspserver and a logitech c920 webcam and a Pi camera. When i stream with the PI camera module the stream is fine over vlc , no issues at all.
When i use the Logitech webcam and stream , and watch the stream on vlc the image smudges and turns grey every few seconds.
This issue is the same over wifi and ethernet.
Any idea what might be the issue ?
my setup:
Pi zero w
Pi camera
logitech c920 webcam

I'm having the same issue on a 3B+ and C920. I don't have a Pi/CSI camera to try.

Hi,
You may try to reduce de resolution or to use RTP over TCP.
Best Regards,
Michel.

I have the same issue and I can provide some additional details:

Raspi camera module works flawlessly (H264)
Some cheap USB camera module from AliExpress works flawlessly (MJPEG)
Logitech C270 (cannot do H264, so MJPEG only):

Works in VLC in MJPG
Green image with some movement in BlueIris (MJPG)

Logitech C920 (can do MJPG and H264):

MJPG:

VLC displays image but colors are way off (like vivid solarized effect)
BlueIris displays Green image with some movement

H264:

VLC displays the bottom 25% of the image correctly (top is garbled)
BlueIris displays the bottom 50% correctly (top is green)

I wonder if the issue is specific to Logitech... :?
I'd like to understand what is going on. I am particularly interested in BlueIris in order to record the streams.
Michel:

You may try to reduce de resolution or to use RTP over TCP.

I did try to set the resolution of the C920 all the way down to 160x120. It did not many any difference (except the bottom 25% of the picture that displays is now very pixellated ;)
I also tried to reduce the framerate to 10fps. No change.
Can you please elaborate on what you mean with "use RTP over TCP" ?  (I used "rtsp://" and I don't know what RTP over TCP would look like)
Thank you for this project and all the time you put into it! :)

Hi @fplanque
RTP over TCP negociation can be set using --rtsp-tcp  argument of VLC.
Best Regards,
Michel.

Tried to use v4l2-ctl and change the output format of the cam?
I think those logitech cams can put out a h264 stream which the rtsp server does not like.
this is what i had to do to make it work...
sleep 10

sudo rmmod v4l2loopback &

sleep 1

sudo modprobe v4l2loopback video_nr=20 &

sleep 2

sudo v4l2-ctl -d /dev/video0 --set-fmt-video=width=800,height=448,pixelformat=YUYV &

sleep 1

sudo v4l2-ctl --set-ctrl focus_auto=0 -d /dev/video0 &

sleep 1

sudo v4l2-ctl --set-ctrl focus_absolute=44 -d /dev/video0 &

sleep 1

sudo v4l2-ctl --set-ctrl sharpness=255 -d /dev/video0 &

sleep 1

sudo v4l2compress_omx /dev/video0 /dev/video20 &


Automated Package Upgrade

:tada: This PR is included in version 28.2.50 :tada:
The release is available on:

npm package (@latest dist-tag)
GitHub release

Your semantic-release bot :package::rocket:


Add default values

Should we add the default values to the spec? This would allow us to completely replace this document (if we want that).

What do you mean? (doc is not found)

Sorry, fixed the link. The idea was to eventually replace the api description in the GH repo with the generated html by swagger.


feat(blockstore): read and write methods

this PR builds on the changes from the insert shreds pr. about 50% of the diff is redundant with that pr's diff

if this branch builds off insert-shreds - can you have it point to merge into the insert-shreds branch instead of main?

closing because it is not possible to change the base branch of a pr


Remove doc/automation.md

The current document is beyond simple revision, being written entirely on the basis of the deprecated brew bundle command. We may rewrite it in the future.

+1


Update gradle wrapper to 7.7.1

Codecov Report

Merging #457 (bd1bb89) into master (7bdb221) will not change coverage.
The diff coverage is n/a.

@@            Coverage Diff            @@
##             master     #457   +/-   ##
=========================================
  Coverage     57.27%   57.27%
  Complexity      789      789
=========================================
  Files            67       67
  Lines          5746     5746
  Branches        854      854
=========================================
  Hits           3291     3291
  Misses         2233     2233
  Partials        222      222

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pages style overrides

Pull Request Test Coverage Report for Build 889095670

0 of 0   changed or added relevant lines in 0 files are covered.
No unchanged relevant lines lost coverage.
Overall coverage remained the same at 81.94%

Totals

Change from base Build 878178791:
0.0%

Covered Lines:
980

Relevant Lines:
1196

💛  - Coveralls

Pull Request Test Coverage Report for Build 889095670
Warning: This coverage report may be inaccurate.
This pull request's base commit is no longer the HEAD commit of its target branch. This means it includes changes from outside the original pull request, including, potentially, unrelated coverage changes.

For more information on this, see Tracking coverage changes with pull request builds.
To avoid this issue with future PRs, see these Recommended CI Configurations.
For a quick fix, rebase this PR at GitHub. Your next report should be accurate.

Details

0 of 0   changed or added relevant lines in 0 files are covered.
No unchanged relevant lines lost coverage.
Overall coverage remained the same at 81.94%

Totals

Change from base Build 878178791:
0.0%

Covered Lines:
980

Relevant Lines:
1196

💛  - Coveralls


S3Mock Configuration Options

We had to requests regarding configuring S3Mock regarding usage of the silent parameter (https://github.com/adobe/S3Mock/issues/76) and Tomcats amount of threads (https://github.com/adobe/S3Mock/issues/75). Today there are some options to configure those (but there's no way to choose the option. So, silent can only be configured programmatically, Tomcat threads can be set via VM argument.
Let's introduce a way to harmonise and open configuration options. When done users can pass their config via environment variable, via VM argument and via command line. This include documentation of existing configuration options.

closing, the two suggestions were implemented, when we need more, we'll open more issues.


Update docs for verbose mode & custom type mapping

This documentation will provide debug steps for unsupported database types. Users can define their type mappings in Laravel's database.php config file. No other changes are needed. This solution works with all supported DB engines and custom (user-defined) data types.
Closes #19 and #16

Great, thanks!


HDDS-7271. Ozone Integration test shows memory leak (graceful shutdown cleanup)

What changes were proposed in this pull request?

Cleanup for RatisDropwizardExports registry on stop/shutdown

Avoiding continuous loop after interrupt for DeleteBlocksCommandHandler

Other services not stopped after stopping the cluster is also handled.

Few cases for "ForkJoinPool" which is based on CompletablFuture can not be handled as part, as this depends on service logic for handling same and marking it close.
These is observed in Ozone integration test
What is the link to the Apache JIRA
https://issues.apache.org/jira/browse/HDDS-7271
How was this patch tested?
This is verified running ozone integration test and verifying heap dump for same. This issue is not observed.

@ChenSammi @nandakumar131 Please review

@ChenSammi please wait for clean CI before merging PRs.  It seems two integration tests are timing out due to this change:
org.apache.hadoop.ozone.dn.ratis.TestDnRatisLogParser
org.apache.hadoop.ozone.container.common.statemachine.commandhandler.TestBlockDeletion

I have reverted the change, please fix the two failing tests and open new PR.


feature/JENKINS-35831 - favorite fix

Related to issue # JENKINS-35381.
Summary of changes:

Fix a bug in Favorite component that caused it to not check correctly if "checked" property changed after initial render

Need to sort out a few other issues before i can verify this is the correct fix. Closing for now.