target mimxrt685s (NXP i.MX RT685): SocTarget has no selected core

Still trying to program the on-board flash of the NXP i.MX RT685EVK through pyOCD; I get an "SoCTarget has no selected core" error.
(NXP.MIMXRT685S_DFP.pdsc modified, removing Pname="cm33")
+ set -e
+ grep DebugPortStart mypack/NXP.MIMXRT685S_DFP.pdsc
          <sequence name="DebugPortStart">
+ cat pyocd_user.py
session.options['debug.log_flm_info'] = True
session.options['allow_no_cores'] = True

def will_connect():
    extFlash = FlashRegion(
               name="flexspi",
               start=0x18000000,
               length=0x800000,
               is_boot_memory=True,
               blocksize=0x1000,
               page_size=0x100,
               flm = "MIMXRT6XX_EVK_FLEXSPI_S.FLM",
            )
    target.memory_map.add_region(extFlash)
+ pyocd flash -v --pack mypack -e chip -t mimxrt685s blinky-mimxrt685_evk_cm33-3.3.0.elf
0010728 W CMSIS-Pack device MIMXRT685S has no identifiable boot memory [cmsis_pack]
0010978 I Target type is mimxrt685s [board]
0014782 I DP IDR = 0x6ba02477 (v2 rev6) [dap]
0014857 I debugvar 'BootTime' = 0x2710 (10000) [pack_target]
0014863 I debugvar 'Dbg_CR' = 0x0 (0) [pack_target]
0014869 I debugvar 'SWO_Pin' = 0x0 (0) [pack_target]
0016292 I AHB-AP#0 IDR = 0x84770001 (AHB-AP var0 rev8) [discovery]
0016388 I AP#2 IDR = 0x002a0000 (AP var0 rev0) [discovery]
0016808 W Skipping CoreSight discovery for AHB-AP#0 because it is disabled [ap]
0016814 E No cores were discovered! [coresight_target]
0016825 I Creating flash algo for region flexspi from: /home/root/nxp/MIMXRT6XX_EVK_FLEXSPI_S.FLM [flm_region_builder]
0017028 I Loading /home/root/nxp/blinky-mimxrt685_evk_cm33-3.3.0.elf [load_cmd]
[                                                  ]   0%0017455 C Error: 'SoCTarget has no selected core' [__main__]

with more logging detail:
0017231 D flash algo: [stack=0x1f850; 0x1f850 b] [b2=0x1f950,+0x1f950] [b1=0x1f850,+0x1f850] [code=0x1fa5c,+0x1fa5c,0x5a4 b] (ram=0x00000000, 0x20000 b) [flash_algo]
0017237 D Running task notify [sequencer]
0017255 I Loading /home/root/nxp/blinky-mimxrt685_evk_cm33-3.3.0.elf [load_cmd]
0017302 D Skipping segment LMA:0x18005598, VMA:0x18005598, size 8 [file_programmer]
0017308 D Writing segment LMA:0x18000000, VMA:0x18000000, size 4912 [file_programmer]
0017325 D Writing segment LMA:0x18001330, VMA:0x30180000, size 256 [file_programmer]
0017332 D Writing segment LMA:0x18001430, VMA:0x18001430, size 18364 [file_programmer]
0017349 D Writing segment LMA:0x18005bec, VMA:0x30180100, size 2386 [file_programmer]
0017365 D Writing segment LMA:0x1800653e, VMA:0x1800653e, size 4 [file_programmer]
0017372 D Skipping segment LMA:0x30180a58, VMA:0x30180a58, size 0 [file_programmer]
0017413 D Using double buffer chip erase program [builder]
0017418 D 0 of 102 pages have erased data [builder]
[                                                  ]   0%0017435 D uninit session <pyocd.core.session.Session object at 0x7fbba39810> [session]
0017441 D uninit board <pyocd.board.board.Board object at 0x7fb9c134d0> [board]
0017831 C Error: 'SoCTarget has no selected core' [__main__]
Traceback (most recent call last):
  File "/usr/lib/python3.11/site-packages/pyocd/__main__.py", line 161, in run
    status = cmd.invoke()
             ^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/subcommands/load_cmd.py", line 130, in invoke
    programmer.program(filename,
  File "/usr/lib/python3.11/site-packages/pyocd/flash/file_programmer.py", line 175, in program
    self._loader.commit()
  File "/usr/lib/python3.11/site-packages/pyocd/flash/loader.py", line 295, in commit
    perf = builder.program(chip_erase=chipErase,
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

This error is because pyocd hasn't been able to successfully find an accessible CPU core. It needs a CPU to run the flash algorithm, and when it tries to access the default core (abstracted by the SoCTarget class's notion of a currently selected core) it, naturally, fails.
I'll keep this issue open for the time being, but at this point it looks like a side effect of other debug sequence issues. For some reason, debug is not being properly unlocked, thus the "Skipping CoreSight discovery for AHB-AP#0 because it is disabled" warning.

I've had some USB host stack issues affecting my tests, with those sorted out and updating to latest PyOCD, the core does seem to be detected, and programming fails with target was not halted as expected after calling flash algorithm routine (IPSR=3).
# pyocd flash --pack ./NXP.MIMXRT685S_DFP.16.0.0 -t mimxrt685s blinky-mimxrt685_evk_cm33-3.3.0.elf
0007439 W CMSIS-Pack device MIMXRT685S has no identifiable boot memory [cmsis_pack]
0011302 I Loading /home/root/mimxrt685evk/blinky-mimxrt685_evk_cm33-3.3.0.elf [load_cmd]
0012667 C target was not halted as expected after calling flash algorithm routine (IPSR=3) [__main__]

Detailed log:
# pyocd --version
0.35.0.dev+gda303b04
+ pyocd list
  #   Probe/Board                                     Unique ID   Target
--------------------------------------------------------------------------
  0   NXP Semiconductors LPC-LINK2 CMSIS-DAP V5.361   NRAQBQHR    n/a
# grep DebugPortStart ./NXP.MIMXRT685S_DFP.16.0.0/NXP.MIMXRT685S_DFP.pdsc
	  <sequence name="DebugPortStart"> <!-- [removed for PyOCD] Pname="cm33" -->
# cat pyocd_user.py
session.options['debug.log_flm_info'] = True
session.options['allow_no_cores'] = True
def will_connect():
    extFlash = FlashRegion(
               name="flexspi",
               start=0x18000000,
               length=0x800000,
               is_boot_memory=True,
               blocksize=0x1000,
               page_size=0x100,
               flm = "MIMXRT6XX_EVK_FLEXSPI_S.FLM",
            )
    target.memory_map.add_region(extFlash)
# pyocd flash -v -vv -Lpyocd.debug.sequences.sequences.trace=debug --pack ./NXP.MIMXRT685S_DFP.16.0.0 -t mimxrt685s blinky-mimxrt685_evk_cm33-3.3.0.elf
0004286 D setting log level debug for ['pyocd.debug.sequences.sequences.trace'] [__main__]
0004430 D Project directory: /home/root/mimxrt685evk [session]
0007379 D Project directory: /home/root/mimxrt685evk [session]
0007381 D Loading user script: /home/root/mimxrt685evk/pyocd_user.py [session]
0007423 D Detaching Kernel Driver of Interface 0 from USB device (VID=1fc9 PID=0090). [pyusb_backend]
0007438 D CMSIS-DAP v1 probe NRAQBQHR: protocol version 1.1.0 [dap_access_cmsis_dap]
0007446 D closing interface [pyusb_backend]
0007520 D MIMXRT685S_DFP DFP (MIMXRT685S): not loading non-default flash algorithm 'arm/MIMXRT6XX_FLEXSPI_B_SFDP_QSPI.FLM' [cmsis_pack]
0007521 D MIMXRT685S_DFP DFP (MIMXRT685S): not loading non-default flash algorithm 'arm/MIMXRT6XX_FLEXSPI_B_SFDP_QSPI_S.FLM' [cmsis_pack]
0007522 W CMSIS-Pack device MIMXRT685S has no identifiable boot memory [cmsis_pack]
0007775 I Target type is mimxrt685s [board]
0007814 D Detaching Kernel Driver of Interface 0 from USB device (VID=1fc9 PID=0090). [pyusb_backend]
0007828 D Running task load_svd [sequencer]
0009791 D Running task pre_connect [sequencer]
0009808 D Running task dp_init [sequencer]
0009814 D Running task lock_probe [sequencer]
0009820 D Running task get_probe_capabilities [sequencer]
0009826 D Running task connect [sequencer]
0009941 D Default wire protocol selected; using SWD [dap]
0009962 D Sending deprecated SWJ sequence to select SWD [swj]
0010046 I DP IDR = 0x6ba02477 (v2 rev6) [dap]
0010051 D Running task clear_sticky_err [sequencer]
0010057 D Running task power_up_debug [sequencer]
0010063 D Running debug sequence 'DebugPortStart' [pack_target]
0010073 D (line 3): decl SWO_Pin = 0x0 [sequences]
0010085 D (line 4): decl Dbg_CR = 0x0 [sequences]
0010090 D (line 5): decl BootTime = 0x2710 [sequences]
0010096 I debugvar 'BootTime' = 0x2710 (10000) [pack_target]
0010102 I debugvar 'Dbg_CR' = 0x0 (0) [pack_target]
0010107 I debugvar 'SWO_Pin' = 0x0 (0) [pack_target]
0010116 D (line 2): decl SW_DP_ABORT = 0x0 [sequences]
0010121 D (line 3): decl DP_CTRL_STAT = 0x4 [sequences]
0010127 D (line 4): decl DP_SELECT = 0x8 [sequences]
0010133 D (line 5): decl powered_down = 0x0 [sequences]
0010139 D (line 7): fn writedp (DP_SELECT{0x8}, 0x0) ... [sequences]
0010160 D (line 7): fn writedp () returned 0x0 [sequences]
0010166 D (line 7): expr stmt = 0x0 [sequences]
0010171 D (line 10): fn readdp (DP_CTRL_STAT{0x4}) ... [sequences]
0010193 D (line 10): fn readdp () returned 0xf40 [sequences]
0010199 D (line 0): 0xf40 & 0xa0000000 -> 0x0 [sequences]
0010204 D (line 0): 0x0 != 0xa0000000 -> 0x1 [sequences]
0010210 D (line 10): powered_down = 0x1 [sequences]
0010216 D (line 1): expr stmt = powered_down{0x1} [sequences]
0010222 D IF(powered_down): pred=1 [sequences]
0010229 D (line 3): fn writedp (DP_CTRL_STAT{0x4}, 0x50000000) ... [sequences]
0010264 D (line 3): fn writedp () returned 0x0 [sequences]
0010270 D (line 3): expr stmt = 0x0 [sequences]
0010277 D (line 1): fn readdp (DP_CTRL_STAT{0x4}) ... [sequences]
0010317 D (line 1): fn readdp () returned 0xf0000040 [sequences]
0010323 D (line 0): 0xf0000040 & 0xa0000000 -> 0xa0000000 [sequences]
0010329 D (line 0): 0xa0000000 != 0xa0000000 -> 0x0 [sequences]
0010334 D (line 1): expr stmt = 0x0 [sequences]
0010340 D WHILE((ReadDP(DP_CTRL_STAT) & 0xA0000000) != 0xA0000000): pred=0 [sequences]
0010347 D (line 0): __protocol{0x10002} & 0xffff -> 0x2 [sequences]
0010352 D (line 0): 0x2 == 0x2 -> 0x1 [sequences]
0010358 D (line 1): expr stmt = 0x1 [sequences]
0010364 D IF((__protocol & 0xFFFF) == 2): pred=1 [sequences]
0010371 D (line 3): fn writedp (DP_CTRL_STAT{0x4}, 0x50000f00) ... [sequences]
0010392 D (line 3): fn writedp () returned 0x0 [sequences]
0010398 D (line 3): expr stmt = 0x0 [sequences]
0010404 D (line 6): fn writedp (SW_DP_ABORT{0x0}, 0x1e) ... [sequences]
0010439 D (line 6): fn writedp () returned 0x0 [sequences]
0010444 D (line 6): expr stmt = 0x0 [sequences]
0010450 D (line 8): fn sequence ('EnableDebugMailbox') ... [sequences]
0010456 D Running debug sub-sequence 'EnableDebugMailbox' [functions]
0010464 D (line 1): fn readap (0x0) ... [sequences]
0010500 D (line 1): fn readap () returned 0x3800052 [sequences]
0010506 D (line 0): 0x3800052 & 0x40 -> 0x40 [sequences]
0010512 D (line 0): ! 0x40 -> 0x0 [sequences]
0010517 D (line 1): expr stmt = 0x0 [sequences]
0010523 D IF(!(ReadAP(0x0) & 0x40)): pred=0 [sequences]
0010529 D Sub-sequence 'EnableDebugMailbox' result = 0 [functions]
0010534 D (line 8): fn sequence () returned 0x0 [sequences]
0010540 D (line 8): expr stmt = 0x0 [sequences]
0010546 D Running task check_version [sequencer]
0010551 D Running task unlock_probe [sequencer]
0010557 D Running task unlock_device [sequencer]
0010563 D Running task create_discoverer [sequencer]
0010568 D Running task discovery [sequencer]
0010574 D Running task find_aps [sequencer]
0010699 D Running task create_aps [sequencer]
0010705 D Running task create_ap.0 [sequencer]
0010776 D AHB-AP#0 default HPROT=3 HNONSEC=0 [ap]
0010811 D AHB-AP#0 implemented HPROT=f HNONSEC=1 [ap]
0010833 I AHB-AP#0 IDR = 0x84770001 (AHB-AP var0 rev8) [discovery]
0010839 D Running task create_ap.2 [sequencer]
0010874 I AP#2 IDR = 0x002a0000 (AP var0 rev0) [discovery]
0010880 D Running task create_ap.3 [sequencer]
0010945 D APB-AP#3 default HPROT=0 HNONSEC=0 [ap]
0010981 D APB-AP#3 implemented HPROT=0 HNONSEC=0 [ap]
0011022 I APB-AP#3 IDR = 0x54770002 (APB-AP var0 rev5) [discovery]
0011028 D Running task find_components [sequencer]
0011033 D Running task init_ap.0 [sequencer]
0011116 I AHB-AP#0 Class 0x1 ROM table #0 @ 0xe00fe000 (designer=015 part=000) [rom_table]
0011173 I [0]<e00ff000:ROM class=1 designer=43b:Arm part=4c9> [rom_table]
0011179 I   AHB-AP#0 Class 0x1 ROM table #1 @ 0xe00ff000 (designer=43b:Arm part=4c9) [rom_table]
0011230 I   [0]<e000e000:SCS M33 class=9 designer=43b:Arm part=d21 devtype=00 archid=2a04 devid=0:0:0> [rom_table]
0011297 I   [1]<e0001000:DWT M33 class=9 designer=43b:Arm part=d21 devtype=00 archid=1a02 devid=0:0:0> [rom_table]
0011347 I   [2]<e0002000:BPU M33 class=9 designer=43b:Arm part=d21 devtype=00 archid=1a03 devid=0:0:0> [rom_table]
0011403 I   [3]<e0000000:ITM M33 class=9 designer=43b:Arm part=d21 devtype=43 archid=1a01 devid=0:0:0> [rom_table]
0011409 D   [4]<fff41002 not present> [rom_table]
0011445 I   [5]<e0041000:ETM M33 class=9 designer=43b:Arm part=d21 devtype=13 archid=4a13 devid=0:0:0> [rom_table]
0011521 I   [6]<e0042000:CTI M33 class=9 designer=43b:Arm part=d21 devtype=14 archid=1a14 devid=40800:0:0> [rom_table]
0011527 D   [7]<fff44002 not present> [rom_table]
0011579 I [1]<e0040000:TPIU M33 class=9 designer=43b:Arm part=d21 devtype=11 archid=0000 devid=ca1:0:0> [rom_table]
0011585 D [2]<1ff02002 not present> [rom_table]
0011591 D [3]<1ff02002 not present> [rom_table]
0011597 D Running task create_cores [sequencer]
0011602 D Creating SCS component [discovery]
0011632 D selected core #0 [soc_target]
0011684 I CPU core #0 is Cortex-M33 r0p3 (security ext present) [cortex_m_v8m]
0011720 I FPU present: FPv5-SP-D16-M [cortex_m]
0011762 D Running task configure_core_reset [sequencer]
0011768 D updated DFP core #0 reset types: {<ResetType.SW_EMULATED: 5>, <ResetType.HW: 1>, <ResetType.SW: 2>, <ResetType.SW_SYSTEM: 3>} [pack_target]
0011774 I Setting core #0 (cm33) default reset sequence to ResetSystem [pack_target]
0011780 D Running task create_components [sequencer]
0011786 D Creating DWT component [discovery]
0011842 I 4 hardware watchpoints [dwt]
0011850 D Creating BPU component [discovery]
0011871 I 8 hardware breakpoints, 1 literal comparators [fpb]
0011878 D fpb has been disabled [fpb]
0011886 D Creating ITM component [discovery]
0011927 D Creating TPIU component [discovery]
0011949 D Running task check_for_cores [sequencer]
0011954 D Running task halt_on_connect [sequencer]
0011960 D halting core 0 [cortex_m]
0011981 D Running task post_connect [sequencer]
0011987 D Running task post_connect_hook [sequencer]
0011992 D Running task create_flash [sequencer]
0012004 I Creating flash algo for region flexspi from: /home/root/mimxrt685evk/MIMXRT6XX_EVK_FLEXSPI_S.FLM [flm_region_builder]
0012161 D Flash algo info: Flash Device:
  name=b'MIMXRT6XX FLEXSPI'
  version=0x101
  type=5
  start=0x18000000
  size=0x4000000
  page_size=0x100
  value_empty=0xff
  prog_timeout_ms=300
  erase_timeout_ms=3000
  sectors:
    start=0x0, size=0x1000
 [flm_region_builder]
0012171 D flash algo: [stack=0x1f850; 0x1f850 b] [b2=0x1f950,+0x1f950] [b1=0x1f850,+0x1f850] [code=0x1fa5c,+0x1fa5c,0x5a4 b] (ram=0x00000000, 0x20000 b) [flash_algo]
0012177 D Running task notify [sequencer]
0012195 I Loading /home/root/mimxrt685evk/blinky-mimxrt685_evk_cm33-3.3.0.elf [load_cmd]
0012234 D Skipping segment LMA:0x18005598, VMA:0x18005598, size 8 [file_programmer]
0012241 D Writing segment LMA:0x18000000, VMA:0x18000000, size 4912 [file_programmer]
0012252 D Writing segment LMA:0x18001330, VMA:0x30180000, size 256 [file_programmer]
0012269 D Writing segment LMA:0x18001430, VMA:0x18001430, size 18364 [file_programmer]
0012280 D Writing segment LMA:0x18005bec, VMA:0x30180100, size 2386 [file_programmer]
0012292 D Writing segment LMA:0x1800653e, VMA:0x1800653e, size 4 [file_programmer]
0012298 D Skipping segment LMA:0x30180a58, VMA:0x30180a58, size 0 [file_programmer]
0012338 D halting core 0 [cortex_m]
0012359 D set reset catch, core 0 [cortex_m]
0012365 D halting core 0 [cortex_m]
0012417 D reset, core 0, type=SW_SYSTEM [cortex_m]
0012423 D Running debug sequence 'ResetSystem' (cm33) [pack_target]
0012440 D (line 2): __dp = 0x0 [sequences]
0012446 D (line 3): __ap = 0x0 [sequences]
0012452 D (line 5): decl SCS_Addr = 0xe000e000 [sequences]
0012457 D (line 0): SCS_Addr{0xe000e000} + 0xd0c -> 0xe000ed0c [sequences]
0012463 D (line 6): decl AIRCR_Addr = 0xe000ed0c [sequences]
0012469 D (line 0): SCS_Addr{0xe000e000} + 0xdf0 -> 0xe000edf0 [sequences]
0012474 D (line 7): decl DHCSR_Addr = 0xe000edf0 [sequences]
0012481 D (line 0): SCS_Addr{0xe000e000} + 0xdfc -> 0xe000edfc [sequences]
0012487 D (line 8): decl DEMCR_Addr = 0xe000edfc [sequences]
0012492 D (line 9): decl tmp = 0 [sequences]
0012498 D (line 11): fn write32 (DHCSR_Addr{0xe000edf0}, 0xa05f0003) ... [sequences]
0012519 D (line 11): fn write32 () returned 0x0 [sequences]
0012525 D (line 11): expr stmt = 0x0 [sequences]
0012531 D (line 13): fn read32 (DEMCR_Addr{0xe000edfc}) ... [sequences]
0012573 D (line 13): fn read32 () returned 0x1100001 [sequences]
0012579 D (line 13): tmp = 0x1100001 [sequences]
0012585 D (line 0): tmp{0x1100001} | 0x1000000 -> 0x1100001 [sequences]
0012590 D (line 14): fn write32 (DEMCR_Addr{0xe000edfc}, 0x1100001) ... [sequences]
0012632 D (line 14): fn write32 () returned 0x0 [sequences]
0012638 D (line 14): expr stmt = 0x0 [sequences]
0012643 D (line 15): fn sequence ('ResetFlash') ... [sequences]
0012649 D Running debug sub-sequence 'ResetFlash' (cm33) [functions]
0012656 D (line 0): __connection{0x1} & 0x1 -> 0x1 [sequences]
0012662 D (line 1): expr stmt = 0x1 [sequences]
0012667 D IF((__connection & 0x01)): pred=1 [sequences]
0012677 D (line 3): fn write32 (0x40004130, 0x130) ... [sequences]
0012698 D (line 3): fn write32 () returned 0x0 [sequences]
0012704 D (line 3): expr stmt = 0x0 [sequences]
0012710 D (line 4): fn write32 (0x40021044, 0x4) ... [sequences]
0012731 D (line 4): fn write32 () returned 0x0 [sequences]
0012737 D (line 4): expr stmt = 0x0 [sequences]
0012743 D (line 5): fn write32 (0x40020074, 0x4) ... [sequences]
0012763 D (line 5): fn write32 () returned 0x0 [sequences]
0012769 D (line 5): expr stmt = 0x0 [sequences]
0012775 D (line 6): fn write32 (0x40102008, 0x1000) ... [sequences]
0012796 D (line 6): fn write32 () returned 0x0 [sequences]
0012802 D (line 6): expr stmt = 0x0 [sequences]
0012808 D (line 7): fn write32 (0x40102288, 0x1000) ... [sequences]
0012829 D (line 7): fn write32 () returned 0x0 [sequences]
0012835 D (line 7): expr stmt = 0x0 [sequences]
0012841 D (line 8): fn dap_delay (0x64) ... [sequences]
0012852 D (line 8): fn dap_delay () returned 0x0 [sequences]
0012857 D (line 8): expr stmt = 0x0 [sequences]
0012863 D (line 9): fn write32 (0x40102208, 0x1000) ... [sequences]
0012884 D (line 9): fn write32 () returned 0x0 [sequences]
0012890 D (line 9): expr stmt = 0x0 [sequences]
0012896 D Sub-sequence 'ResetFlash' result = 0 [functions]
0012902 D (line 15): fn sequence () returned 0x0 [sequences]
0012907 D (line 15): expr stmt = 0x0 [sequences]
0012913 D (line 17): fn write32 (0xe0001020, 0x50002034) ... [sequences]
0012934 D (line 17): fn write32 () returned 0x0 [sequences]
0012940 D (line 17): expr stmt = 0x0 [sequences]
0012946 D (line 18): fn write32 (0xe0001028, 0x814) ... [sequences]
0012967 D (line 18): fn write32 () returned 0x0 [sequences]
0012972 D (line 18): expr stmt = 0x0 [sequences]
0012978 D (line 19): __errorcontrol = 0x1 [sequences]
0012984 D (line 21): fn write32 (AIRCR_Addr{0xe000ed0c}, 0x5fa0004) ... [sequences]
0013005 D Write32(0xe000ed0c) ignored TransferFaultError() because __errorcontrol is set [functions]
0013011 D (line 21): fn write32 () returned 0x0 [sequences]
0013017 D (line 21): expr stmt = 0x0 [sequences]
0013023 D (line 22): fn sequence ('WaitForStopAfterReset') ... [sequences]
0013028 D Running debug sub-sequence 'WaitForStopAfterReset' (cm33) [functions]
0013035 D (line 2): decl SCS_Addr = 0xe000e000 [sequences]
0013041 D (line 0): SCS_Addr{0xe000e000} + 0xdf0 -> 0xe000edf0 [sequences]
0013047 D (line 3): decl DHCSR_Addr = 0xe000edf0 [sequences]
0013053 D (line 0): SCS_Addr{0xe000e000} + 0xd30 -> 0xe000ed30 [sequences]
0013058 D (line 4): decl DFSR_Addr = 0xe000ed30 [sequences]
0013065 D (line 1): fn readap (0x0) ... [sequences]
0013087 D ReadAP(0x00000000) ignored TransferFaultError() because __errorcontrol is set [functions]
0013092 D (line 1): fn readap () returned 0x0 [sequences]
0013098 D (line 0): 0x0 & 0x40 -> 0x0 [sequences]
0013104 D (line 0): 0x0 == 0x0 -> 0x1 [sequences]
0013109 D (line 1): expr stmt = 0x1 [sequences]
0013115 D WHILE((ReadAP(0) & 0x40) == 0): pred=1 [sequences]
0013121 D (line 1): fn readap (0x0) ... [sequences]
0013157 D (line 1): fn readap () returned 0x3800052 [sequences]
0013163 D (line 0): 0x3800052 & 0x40 -> 0x40 [sequences]
0013168 D (line 0): 0x40 == 0x0 -> 0x0 [sequences]
0013174 D (line 1): expr stmt = 0x0 [sequences]
0013180 D WHILE((ReadAP(0) & 0x40) == 0): pred=0 [sequences]
0013188 D (line 2): fn sequence ('EnableDebugMailbox') ... [sequences]
0013193 D Running debug sub-sequence 'EnableDebugMailbox' (cm33) [functions]
0013201 D (line 1): fn readap (0x0) ... [sequences]
0013222 D (line 1): fn readap () returned 0x3800052 [sequences]
0013228 D (line 0): 0x3800052 & 0x40 -> 0x40 [sequences]
0013234 D (line 0): ! 0x40 -> 0x0 [sequences]
0013239 D (line 1): expr stmt = 0x0 [sequences]
0013245 D IF(!(ReadAP(0x0) & 0x40)): pred=0 [sequences]
0013251 D Sub-sequence 'EnableDebugMailbox' result = 0 [functions]
0013256 D (line 2): fn sequence () returned 0x0 [sequences]
0013262 D (line 2): expr stmt = 0x0 [sequences]
0013268 D (line 3): fn write32 (DHCSR_Addr{0xe000edf0}, 0xa05f0003) ... [sequences]
0013288 D (line 3): fn write32 () returned 0x0 [sequences]
0013293 D (line 3): expr stmt = 0x0 [sequences]
0013299 D (line 5): fn write32 (0xe0001020, 0x0) ... [sequences]
0013319 D (line 5): fn write32 () returned 0x0 [sequences]
0013325 D (line 5): expr stmt = 0x0 [sequences]
0013330 D (line 6): fn write32 (0xe0001028, 0x0) ... [sequences]
0013443 D (line 6): fn write32 () returned 0x0 [sequences]
0013444 D (line 6): expr stmt = 0x0 [sequences]
0013444 D Sub-sequence 'WaitForStopAfterReset' result = 0 [functions]
0013445 D (line 22): fn sequence () returned 0x0 [sequences]
0013445 D (line 22): expr stmt = 0x0 [sequences]
0013446 D (line 23): __errorcontrol = 0x0 [sequences]
0013481 D clear reset catch, core 0 [cortex_m]
0013525 D resuming core 0 [cortex_m]
0013525 D added=[] removed=[] [manager]
0013526 D bps after flush={} [manager]
0013534 D halting core 0 [cortex_m]
0013545 D halting core 0 [cortex_m]
0013569 D resuming core 0 [cortex_m]
0013569 D added=[] removed=[] [manager]
0013570 D bps after flush={} [manager]
0013577 D halting core 0 [cortex_m]
0013589 D uninit session <pyocd.core.session.Session object at 0x7fba662550> [session]
0013590 D uninit board <pyocd.board.board.Board object at 0x7fb9ff26d0> [board]
0013594 D resuming core 0 [cortex_m]
0013595 D added=[] removed=[] [manager]
0013595 D bps after flush={} [manager]
0013609 D closing interface [pyusb_backend]
0013633 C target was not halted as expected after calling flash algorithm routine (IPSR=3) [__main__]
Traceback (most recent call last):
  File "/usr/lib/python3.11/site-packages/pyocd/flash/builder.py", line 259, in _enable_read_access
    self.flash.init(self.flash.Operation.VERIFY)
  File "/usr/lib/python3.11/site-packages/pyocd/flash/flash.py", line 253, in init
    result = self._call_function_and_wait(self.flash_algo['pc_init'],
             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/flash/flash.py", line 676, in _call_function_and_wait
    return self.wait_for_completion(timeout=timeout)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/flash/flash.py", line 663, in wait_for_completion
    raise exceptions.FlashFailure("target was not halted as expected after calling "
pyocd.core.exceptions.FlashFailure: target was not halted as expected after calling flash algorithm routine (IPSR=3)

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "/usr/lib/python3.11/site-packages/pyocd/__main__.py", line 161, in run
    status = cmd.invoke()
             ^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/subcommands/load_cmd.py", line 130, in invoke
    programmer.program(filename,
  File "/usr/lib/python3.11/site-packages/pyocd/flash/file_programmer.py", line 175, in program
    self._loader.commit()
  File "/usr/lib/python3.11/site-packages/pyocd/flash/loader.py", line 295, in commit
    perf = builder.program(chip_erase=chipErase,
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/flash/builder.py", line 492, in program
    sector_erase_count, page_program_time = self._compute_sector_erase_pages_and_weight(fast_verify)
                                            ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/flash/builder.py", line 673, in _compute_sector_erase_pages_and_weight
    self._analyze_pages_with_partial_read()
  File "/usr/lib/python3.11/site-packages/pyocd/flash/builder.py", line 608, in _analyze_pages_with_partial_read
    self._enable_read_access()
  File "/usr/lib/python3.11/site-packages/pyocd/flash/builder.py", line 262, in _enable_read_access
    self.flash.init(self.flash.Operation.ERASE)
  File "/usr/lib/python3.11/site-packages/pyocd/flash/flash.py", line 253, in init
    result = self._call_function_and_wait(self.flash_algo['pc_init'],
             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/flash/flash.py", line 676, in _call_function_and_wait
    return self.wait_for_completion(timeout=timeout)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/flash/flash.py", line 663, in wait_for_completion
    raise exceptions.FlashFailure("target was not halted as expected after calling "
pyocd.core.exceptions.FlashFailure: target was not halted as expected after calling flash algorithm routine (IPSR=3)

Same outcome, but different debug logs, when using the unmodified pack file:
# pyocd flash -v -vv -Lpyocd.debug.sequences.sequences.trace=debug --pack ./NXP.MIMXRT685S_DFP.16.0.0.pack -t mimxrt685s blinky-mimxrt685_evk_cm33-3.3.0.elf
0004299 D setting log level debug for ['pyocd.debug.sequences.sequences.trace'] [__main__]
0004443 D Project directory: /home/root/mimxrt685evk [session]
0007363 D Project directory: /home/root/mimxrt685evk [session]
0007366 D Loading user script: /home/root/mimxrt685evk/pyocd_user.py [session]
0007407 D Detaching Kernel Driver of Interface 0 from USB device (VID=1fc9 PID=0090). [pyusb_backend]
0007424 D CMSIS-DAP v1 probe NRAQBQHR: protocol version 1.1.0 [dap_access_cmsis_dap]
0007431 D closing interface [pyusb_backend]
0007545 D MIMXRT685S_DFP DFP (MIMXRT685S): not loading non-default flash algorithm 'arm/MIMXRT6XX_FLEXSPI_B_SFDP_QSPI.FLM' [cmsis_pack]
0007546 D MIMXRT685S_DFP DFP (MIMXRT685S): not loading non-default flash algorithm 'arm/MIMXRT6XX_FLEXSPI_B_SFDP_QSPI_S.FLM' [cmsis_pack]
0007546 W CMSIS-Pack device MIMXRT685S has no identifiable boot memory [cmsis_pack]
0007851 I Target type is mimxrt685s [board]
0007891 D Detaching Kernel Driver of Interface 0 from USB device (VID=1fc9 PID=0090). [pyusb_backend]
0007904 D Running task load_svd [sequencer]
0009847 D Running task pre_connect [sequencer]
0009864 D Running task dp_init [sequencer]
0009870 D Running task lock_probe [sequencer]
0009877 D Running task get_probe_capabilities [sequencer]
0009883 D Running task connect [sequencer]
0009975 D Default wire protocol selected; using SWD [dap]
0010010 D Sending deprecated SWJ sequence to select SWD [swj]
0010129 I DP IDR = 0x6ba02477 (v2 rev6) [dap]
0010135 D Running task clear_sticky_err [sequencer]
0010141 D Running task power_up_debug [sequencer]
0010168 D Running task check_version [sequencer]
0010173 D Running task unlock_probe [sequencer]
0010179 D Running task unlock_device [sequencer]
0010185 D Running task create_discoverer [sequencer]
0010191 D Running task discovery [sequencer]
0010196 D Running task find_aps [sequencer]
0010380 D Running task create_aps [sequencer]
0010386 D Running task create_ap.0 [sequencer]
0010454 D AHB-AP#0 default HPROT=3 HNONSEC=0 [ap]
0010474 D AHB-AP#0 implemented HPROT=f HNONSEC=1 [ap]
0010496 I AHB-AP#0 IDR = 0x84770001 (AHB-AP var0 rev8) [discovery]
0010502 D Running task create_ap.2 [sequencer]
0010522 I AP#2 IDR = 0x002a0000 (AP var0 rev0) [discovery]
0010528 D Running task create_ap.3 [sequencer]
0010624 D APB-AP#3 default HPROT=0 HNONSEC=0 [ap]
0010645 D APB-AP#3 implemented HPROT=0 HNONSEC=0 [ap]
0010686 I APB-AP#3 IDR = 0x54770002 (APB-AP var0 rev5) [discovery]
0010692 D Running task find_components [sequencer]
0010698 D Running task init_ap.0 [sequencer]
0010790 I AHB-AP#0 Class 0x1 ROM table #0 @ 0xe00fe000 (designer=015 part=000) [rom_table]
0010841 I [0]<e00ff000:ROM class=1 designer=43b:Arm part=4c9> [rom_table]
0010847 I   AHB-AP#0 Class 0x1 ROM table #1 @ 0xe00ff000 (designer=43b:Arm part=4c9) [rom_table]
0010933 I   [0]<e000e000:SCS M33 class=9 designer=43b:Arm part=d21 devtype=00 archid=2a04 devid=0:0:0> [rom_table]
0010999 I   [1]<e0001000:DWT M33 class=9 designer=43b:Arm part=d21 devtype=00 archid=1a02 devid=0:0:0> [rom_table]
0011035 I   [2]<e0002000:BPU M33 class=9 designer=43b:Arm part=d21 devtype=00 archid=1a03 devid=0:0:0> [rom_table]
0011071 I   [3]<e0000000:ITM M33 class=9 designer=43b:Arm part=d21 devtype=43 archid=1a01 devid=0:0:0> [rom_table]
0011076 D   [4]<fff41002 not present> [rom_table]
0011112 I   [5]<e0041000:ETM M33 class=9 designer=43b:Arm part=d21 devtype=13 archid=4a13 devid=0:0:0> [rom_table]
0011148 I   [6]<e0042000:CTI M33 class=9 designer=43b:Arm part=d21 devtype=14 archid=1a14 devid=40800:0:0> [rom_table]
0011153 D   [7]<fff44002 not present> [rom_table]
0011204 I [1]<e0040000:TPIU M33 class=9 designer=43b:Arm part=d21 devtype=11 archid=0000 devid=ca1:0:0> [rom_table]
0011210 D [2]<1ff02002 not present> [rom_table]
0011215 D [3]<1ff02002 not present> [rom_table]
0011221 D Running task create_cores [sequencer]
0011227 D Creating SCS component [discovery]
0011257 D selected core #0 [soc_target]
0011309 I CPU core #0 is Cortex-M33 r0p3 (security ext present) [cortex_m_v8m]
0011359 I FPU present: FPv5-SP-D16-M [cortex_m]
0011422 D Running task configure_core_reset [sequencer]
0011428 D updated DFP core #0 reset types: {<ResetType.HW: 1>, <ResetType.SW_EMULATED: 5>, <ResetType.SW_SYSTEM: 3>, <ResetType.SW: 2>} [pack_target]
0011433 I Setting core #0 (cm33) default reset sequence to ResetSystem [pack_target]
0011449 D Running task create_components [sequencer]
0011455 D Creating DWT component [discovery]
0011507 I 4 hardware watchpoints [dwt]
0011515 D Creating BPU component [discovery]
0011557 I 8 hardware breakpoints, 1 literal comparators [fpb]
0011564 D fpb has been disabled [fpb]
0011572 D Creating ITM component [discovery]
0011622 D Creating TPIU component [discovery]
0011644 D Running task check_for_cores [sequencer]
0011649 D Running task halt_on_connect [sequencer]
0011655 D halting core 0 [cortex_m]
0011676 D Running task post_connect [sequencer]
0011681 D Running task post_connect_hook [sequencer]
0011687 D Running task create_flash [sequencer]
0011698 I Creating flash algo for region flexspi from: /home/root/mimxrt685evk/MIMXRT6XX_EVK_FLEXSPI_S.FLM [flm_region_builder]
0011855 D Flash algo info: Flash Device:
  name=b'MIMXRT6XX FLEXSPI'
  version=0x101
  type=5
  start=0x18000000
  size=0x4000000
  page_size=0x100
  value_empty=0xff
  prog_timeout_ms=300
  erase_timeout_ms=3000
  sectors:
    start=0x0, size=0x1000
 [flm_region_builder]
0011863 D flash algo: [stack=0x1f850; 0x1f850 b] [b2=0x1f950,+0x1f950] [b1=0x1f850,+0x1f850] [code=0x1fa5c,+0x1fa5c,0x5a4 b] (ram=0x00000000, 0x20000 b) [flash_algo]
0011870 D Running task notify [sequencer]
0011887 I Loading /home/root/mimxrt685evk/blinky-mimxrt685_evk_cm33-3.3.0.elf [load_cmd]
0011937 D Skipping segment LMA:0x18005598, VMA:0x18005598, size 8 [file_programmer]
0011948 D Writing segment LMA:0x18000000, VMA:0x18000000, size 4912 [file_programmer]
0011959 D Writing segment LMA:0x18001330, VMA:0x30180000, size 256 [file_programmer]
0011981 D Writing segment LMA:0x18001430, VMA:0x18001430, size 18364 [file_programmer]
0011998 D Writing segment LMA:0x18005bec, VMA:0x30180100, size 2386 [file_programmer]
0012009 D Writing segment LMA:0x1800653e, VMA:0x1800653e, size 4 [file_programmer]
0012016 D Skipping segment LMA:0x30180a58, VMA:0x30180a58, size 0 [file_programmer]
0012055 D halting core 0 [cortex_m]
0012077 D set reset catch, core 0 [cortex_m]
0012083 D halting core 0 [cortex_m]
0012130 D reset, core 0, type=SW_SYSTEM [cortex_m]
0012137 D Running debug sequence 'ResetSystem' (cm33) [pack_target]
0012147 D (line 3): decl SWO_Pin = 0x0 [sequences]
0012153 D (line 4): decl Dbg_CR = 0x0 [sequences]
0012159 D (line 5): decl BootTime = 0x2710 [sequences]
0012164 I debugvar 'BootTime' = 0x2710 (10000) [pack_target]
0012170 I debugvar 'Dbg_CR' = 0x0 (0) [pack_target]
0012176 I debugvar 'SWO_Pin' = 0x0 (0) [pack_target]
0012193 D (line 2): __dp = 0x0 [sequences]
0012199 D (line 3): __ap = 0x0 [sequences]
0012204 D (line 5): decl SCS_Addr = 0xe000e000 [sequences]
0012210 D (line 0): SCS_Addr{0xe000e000} + 0xd0c -> 0xe000ed0c [sequences]
0012216 D (line 6): decl AIRCR_Addr = 0xe000ed0c [sequences]
0012222 D (line 0): SCS_Addr{0xe000e000} + 0xdf0 -> 0xe000edf0 [sequences]
0012227 D (line 7): decl DHCSR_Addr = 0xe000edf0 [sequences]
0012233 D (line 0): SCS_Addr{0xe000e000} + 0xdfc -> 0xe000edfc [sequences]
0012239 D (line 8): decl DEMCR_Addr = 0xe000edfc [sequences]
0012244 D (line 9): decl tmp = 0 [sequences]
0012250 D (line 11): fn write32 (DHCSR_Addr{0xe000edf0}, 0xa05f0003) ... [sequences]
0012277 D (line 11): fn write32 () returned 0x0 [sequences]
0012282 D (line 11): expr stmt = 0x0 [sequences]
0012288 D (line 13): fn read32 (DEMCR_Addr{0xe000edfc}) ... [sequences]
0012315 D (line 13): fn read32 () returned 0x1100001 [sequences]
0012331 D (line 13): tmp = 0x1100001 [sequences]
0012332 D (line 0): tmp{0x1100001} | 0x1000000 -> 0x1100001 [sequences]
0012338 D (line 14): fn write32 (DEMCR_Addr{0xe000edfc}, 0x1100001) ... [sequences]
0012364 D (line 14): fn write32 () returned 0x0 [sequences]
0012370 D (line 14): expr stmt = 0x0 [sequences]
0012376 D (line 15): fn sequence ('ResetFlash') ... [sequences]
0012381 D Running debug sub-sequence 'ResetFlash' (cm33) [functions]
0012388 D (line 0): __connection{0x1} & 0x1 -> 0x1 [sequences]
0012394 D (line 1): expr stmt = 0x1 [sequences]
0012399 D IF((__connection & 0x01)): pred=1 [sequences]
0012409 D (line 3): fn write32 (0x40004130, 0x130) ... [sequences]
0012430 D (line 3): fn write32 () returned 0x0 [sequences]
0012436 D (line 3): expr stmt = 0x0 [sequences]
0012442 D (line 4): fn write32 (0x40021044, 0x4) ... [sequences]
0012468 D (line 4): fn write32 () returned 0x0 [sequences]
0012474 D (line 4): expr stmt = 0x0 [sequences]
0012479 D (line 5): fn write32 (0x40020074, 0x4) ... [sequences]
0012506 D (line 5): fn write32 () returned 0x0 [sequences]
0012512 D (line 5): expr stmt = 0x0 [sequences]
0012518 D (line 6): fn write32 (0x40102008, 0x1000) ... [sequences]
0012544 D (line 6): fn write32 () returned 0x0 [sequences]
0012550 D (line 6): expr stmt = 0x0 [sequences]
0012556 D (line 7): fn write32 (0x40102288, 0x1000) ... [sequences]
0012582 D (line 7): fn write32 () returned 0x0 [sequences]
0012588 D (line 7): expr stmt = 0x0 [sequences]
0012594 D (line 8): fn dap_delay (0x64) ... [sequences]
0012605 D (line 8): fn dap_delay () returned 0x0 [sequences]
0012611 D (line 8): expr stmt = 0x0 [sequences]
0012617 D (line 9): fn write32 (0x40102208, 0x1000) ... [sequences]
0012643 D (line 9): fn write32 () returned 0x0 [sequences]
0012649 D (line 9): expr stmt = 0x0 [sequences]
0012655 D Sub-sequence 'ResetFlash' result = 0 [functions]
0012661 D (line 15): fn sequence () returned 0x0 [sequences]
0012666 D (line 15): expr stmt = 0x0 [sequences]
0012672 D (line 17): fn write32 (0xe0001020, 0x50002034) ... [sequences]
0012698 D (line 17): fn write32 () returned 0x0 [sequences]
0012698 D (line 17): expr stmt = 0x0 [sequences]
0012699 D (line 18): fn write32 (0xe0001028, 0x814) ... [sequences]
0012718 D (line 18): fn write32 () returned 0x0 [sequences]
0012724 D (line 18): expr stmt = 0x0 [sequences]
0012730 D (line 19): __errorcontrol = 0x1 [sequences]
0012736 D (line 21): fn write32 (AIRCR_Addr{0xe000ed0c}, 0x5fa0004) ... [sequences]
0012761 D Write32(0xe000ed0c) ignored TransferFaultError() because __errorcontrol is set [functions]
0012767 D (line 21): fn write32 () returned 0x0 [sequences]
0012773 D (line 21): expr stmt = 0x0 [sequences]
0012779 D (line 22): fn sequence ('WaitForStopAfterReset') ... [sequences]
0012785 D Running debug sub-sequence 'WaitForStopAfterReset' (cm33) [functions]
0012791 D (line 2): decl SCS_Addr = 0xe000e000 [sequences]
0012797 D (line 0): SCS_Addr{0xe000e000} + 0xdf0 -> 0xe000edf0 [sequences]
0012803 D (line 3): decl DHCSR_Addr = 0xe000edf0 [sequences]
0012809 D (line 0): SCS_Addr{0xe000e000} + 0xd30 -> 0xe000ed30 [sequences]
0012814 D (line 4): decl DFSR_Addr = 0xe000ed30 [sequences]
0012821 D (line 1): fn readap (0x0) ... [sequences]
0012848 D ReadAP(0x00000000) ignored TransferFaultError() because __errorcontrol is set [functions]
0012854 D (line 1): fn readap () returned 0x0 [sequences]
0012860 D (line 0): 0x0 & 0x40 -> 0x0 [sequences]
0012865 D (line 0): 0x0 == 0x0 -> 0x1 [sequences]
0012871 D (line 1): expr stmt = 0x1 [sequences]
0012877 D WHILE((ReadAP(0) & 0x40) == 0): pred=1 [sequences]
0012882 D (line 1): fn readap (0x0) ... [sequences]
0012909 D (line 1): fn readap () returned 0x3800052 [sequences]
0012915 D (line 0): 0x3800052 & 0x40 -> 0x40 [sequences]
0012920 D (line 0): 0x40 == 0x0 -> 0x0 [sequences]
0012926 D (line 1): expr stmt = 0x0 [sequences]
0012932 D WHILE((ReadAP(0) & 0x40) == 0): pred=0 [sequences]
0012940 D (line 2): fn sequence ('EnableDebugMailbox') ... [sequences]
0012946 D Running debug sub-sequence 'EnableDebugMailbox' (cm33) [functions]
0012953 D (line 1): fn readap (0x0) ... [sequences]
0012979 D (line 1): fn readap () returned 0x3800052 [sequences]
0012985 D (line 0): 0x3800052 & 0x40 -> 0x40 [sequences]
0012991 D (line 0): ! 0x40 -> 0x0 [sequences]
0012996 D (line 1): expr stmt = 0x0 [sequences]
0013002 D IF(!(ReadAP(0x0) & 0x40)): pred=0 [sequences]
0013008 D Sub-sequence 'EnableDebugMailbox' result = 0 [functions]
0013013 D (line 2): fn sequence () returned 0x0 [sequences]
0013019 D (line 2): expr stmt = 0x0 [sequences]
0013025 D (line 3): fn write32 (DHCSR_Addr{0xe000edf0}, 0xa05f0003) ... [sequences]
0013046 D (line 3): fn write32 () returned 0x0 [sequences]
0013052 D (line 3): expr stmt = 0x0 [sequences]
0013057 D (line 5): fn write32 (0xe0001020, 0x0) ... [sequences]
0013084 D (line 5): fn write32 () returned 0x0 [sequences]
0013090 D (line 5): expr stmt = 0x0 [sequences]
0013096 D (line 6): fn write32 (0xe0001028, 0x0) ... [sequences]
0013122 D (line 6): fn write32 () returned 0x0 [sequences]
0013128 D (line 6): expr stmt = 0x0 [sequences]
0013133 D Sub-sequence 'WaitForStopAfterReset' result = 0 [functions]
0013139 D (line 22): fn sequence () returned 0x0 [sequences]
0013145 D (line 22): expr stmt = 0x0 [sequences]
0013150 D (line 23): __errorcontrol = 0x0 [sequences]
0013309 D clear reset catch, core 0 [cortex_m]
0013437 D resuming core 0 [cortex_m]
0013542 D added=[] removed=[] [manager]
0013543 D bps after flush={} [manager]
0013551 D halting core 0 [cortex_m]
0013563 D halting core 0 [cortex_m]
0013587 D resuming core 0 [cortex_m]
0013588 D added=[] removed=[] [manager]
0013588 D bps after flush={} [manager]
0013596 D halting core 0 [cortex_m]
0013607 D uninit session <pyocd.core.session.Session object at 0x7f899332d0> [session]
0013608 D uninit board <pyocd.board.board.Board object at 0x7f8d4dbb10> [board]
0013613 D resuming core 0 [cortex_m]
0013614 D added=[] removed=[] [manager]
0013614 D bps after flush={} [manager]
0013629 D closing interface [pyusb_backend]
0013653 C target was not halted as expected after calling flash algorithm routine (IPSR=3) [__main__]
Traceback (most recent call last):
  File "/usr/lib/python3.11/site-packages/pyocd/flash/builder.py", line 259, in _enable_read_access
    self.flash.init(self.flash.Operation.VERIFY)
  File "/usr/lib/python3.11/site-packages/pyocd/flash/flash.py", line 253, in init
    result = self._call_function_and_wait(self.flash_algo['pc_init'],
             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/flash/flash.py", line 676, in _call_function_and_wait
    return self.wait_for_completion(timeout=timeout)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/flash/flash.py", line 663, in wait_for_completion
    raise exceptions.FlashFailure("target was not halted as expected after calling "
pyocd.core.exceptions.FlashFailure: target was not halted as expected after calling flash algorithm routine (IPSR=3)

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "/usr/lib/python3.11/site-packages/pyocd/__main__.py", line 161, in run
    status = cmd.invoke()
             ^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/subcommands/load_cmd.py", line 130, in invoke
    programmer.program(filename,
  File "/usr/lib/python3.11/site-packages/pyocd/flash/file_programmer.py", line 175, in program
    self._loader.commit()
  File "/usr/lib/python3.11/site-packages/pyocd/flash/loader.py", line 295, in commit
    perf = builder.program(chip_erase=chipErase,
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/flash/builder.py", line 492, in program
    sector_erase_count, page_program_time = self._compute_sector_erase_pages_and_weight(fast_verify)
                                            ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/flash/builder.py", line 673, in _compute_sector_erase_pages_and_weight
    self._analyze_pages_with_partial_read()
  File "/usr/lib/python3.11/site-packages/pyocd/flash/builder.py", line 608, in _analyze_pages_with_partial_read
    self._enable_read_access()
  File "/usr/lib/python3.11/site-packages/pyocd/flash/builder.py", line 262, in _enable_read_access
    self.flash.init(self.flash.Operation.ERASE)
  File "/usr/lib/python3.11/site-packages/pyocd/flash/flash.py", line 253, in init
    result = self._call_function_and_wait(self.flash_algo['pc_init'],
             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/flash/flash.py", line 676, in _call_function_and_wait
    return self.wait_for_completion(timeout=timeout)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/site-packages/pyocd/flash/flash.py", line 663, in wait_for_completion
    raise exceptions.FlashFailure("target was not halted as expected after calling "
pyocd.core.exceptions.FlashFailure: target was not halted as expected after calling flash algorithm routine (IPSR=3)

What does work, is using PyOCD (without CMSIS pack) with NXP's SPSDK, to put the i.MX RT685 in serial download mode:
# nxpdebugmbox -i pyocd -v -vv ispmode -m 0
  #   Interface   Id         Description
----------------------------------------------------------------------------
  0   PyOCD       NRAQBQHR   NXP Semiconductors LPC-LINK2 CMSIS-DAP V5.361
DEBUG:spsdk.debuggers.debug_probe_pyocd:The SPSDK PyOCD Interface has been initialized (10701ms since start, debug_probe_pyocd.py:66)
DEBUG:pyocd.core.session:Project directory: /home/root
DEBUG:pyocd.core.session:Project directory: /home/root
DEBUG:pyocd.probe.pydapaccess.interface.pyusb_backend:Detaching Kernel Driver of Interface 0 from USB device (VID=1fc9 PID=0090).
DEBUG:pyocd.probe.pydapaccess.dap_access_cmsis_dap:CMSIS-DAP v1 probe NRAQBQHR: protocol version 1.1.0
DEBUG:pyocd.probe.pydapaccess.interface.pyusb_backend:closing interface
DEBUG:pyocd.coresight.coresight_target:Using default Cortex-M memory map (no memory map supplied)
DEBUG:pyocd.probe.pydapaccess.interface.pyusb_backend:Detaching Kernel Driver of Interface 0 from USB device (VID=1fc9 PID=0090).
DEBUG:pyocd.probe.swj:Sending deprecated SWJ sequence to select SWD
DEBUG:spsdk.debuggers.debug_probe_pyocd:DPIDR(idr=1805657207, partno=186, version=2, revision=6, mindp=False) (10924ms since start, debug_probe_pyocd.py:119)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight read DP, address: 00000004, data: F0000F40 (10928ms since start, debug_probe_pyocd.py:190)
DEBUG:spsdk.debuggers.debug_probe:Checked Sticky Errors: 0xf0000f40 (10928ms since start, debug_probe.py:283)
DEBUG:spsdk.debuggers.debug_probe:Power up the debug connection (10929ms since start, debug_probe.py:361)
DEBUG:spsdk.debuggers.debug_probe:Power Control the debug connection:
System power: True
Debug power: True (10929ms since start, debug_probe.py:334)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight write DP, address: 00000004, data: 50000F00 (10930ms since start, debug_probe_pyocd.py:220)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight read DP, address: 00000004, data: F0000F40 (10934ms since start, debug_probe_pyocd.py:190)
INFO:spsdk.debuggers.debug_probe_pyocd:PyOCD connected via LPC-LINK2 CMSIS-DAP V5.361 probe.
DEBUG:spsdk.dat.debug_mailbox:Reset mode: True (10935ms since start, debug_mailbox.py:66)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight write DP, address: 00000008, data: 000000F0 (10936ms since start, debug_probe_pyocd.py:220)
DEBUG:spsdk.debuggers.debug_probe:Selected AP: 0, Bank: 0xf (10936ms since start, debug_probe.py:382)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight read AP, address: 0000000C, data: 84770001 (10940ms since start, debug_probe_pyocd.py:190)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight write DP, address: 00000008, data: 020000F0 (10941ms since start, debug_probe_pyocd.py:220)
DEBUG:spsdk.debuggers.debug_probe:Selected AP: 2, Bank: 0xf (10941ms since start, debug_probe.py:382)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight read AP, address: 0000000C, data: 002A0000 (10945ms since start, debug_probe_pyocd.py:190)
DEBUG:spsdk.dat.debug_mailbox:Found debug mailbox access port at AP2, IDR: 0x002A0000 (10945ms since start, debug_mailbox.py:190)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight write DP, address: 00000008, data: 02000000 (10946ms since start, debug_probe_pyocd.py:220)
DEBUG:spsdk.debuggers.debug_probe:Selected AP: 2, Bank: 0x0 (10946ms since start, debug_probe.py:382)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight write AP, address: 00000000, data: 00000021 (10947ms since start, debug_probe_pyocd.py:220)
DEBUG:spsdk.debuggers.debug_probe:Trying to re-initialize debug connection (10951ms since start, debug_probe.py:319)
DEBUG:spsdk.debuggers.debug_probe:Power down the debug connection (10952ms since start, debug_probe.py:367)
DEBUG:spsdk.debuggers.debug_probe:Power Control the debug connection:
System power: False
Debug power: True (10952ms since start, debug_probe.py:334)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight write DP, address: 00000004, data: 10000F00 (10953ms since start, debug_probe_pyocd.py:220)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight read DP, address: 00000004, data: 30000F00 (10956ms since start, debug_probe_pyocd.py:190)
DEBUG:spsdk.debuggers.debug_probe:Power Control the debug connection:
System power: False
Debug power: False (10957ms since start, debug_probe.py:334)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight write DP, address: 00000004, data: 00000F00 (10957ms since start, debug_probe_pyocd.py:220)
DEBUG:spsdk.debuggers.debug_probe:Power up the debug connection (10958ms since start, debug_probe.py:361)
DEBUG:spsdk.debuggers.debug_probe:Power Control the debug connection:
System power: True
Debug power: True (10958ms since start, debug_probe.py:334)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight write DP, address: 00000004, data: 50000F00 (10959ms since start, debug_probe_pyocd.py:220)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight read DP, address: 00000004, data: F0000F00 (10963ms since start, debug_probe_pyocd.py:190)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight read DP, address: 00000004, data: F0000F00 (10966ms since start, debug_probe_pyocd.py:190)
DEBUG:spsdk.debuggers.debug_probe:Checked Sticky Errors: 0xf0000f00 (10966ms since start, debug_probe.py:283)
DEBUG:spsdk.debuggers.debug_probe:Debug interface: Read OK fail detected:

  - READOK: Read operation failed (10967ms since start, debug_probe.py:299)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight write DP, address: 00000000, data: 0000001F (10967ms since start, debug_probe_pyocd.py:220)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight write DP, address: 00000008, data: 02000000 (11018ms since start, debug_probe_pyocd.py:220)
DEBUG:spsdk.debuggers.debug_probe:Selected AP: 2, Bank: 0x0 (11019ms since start, debug_probe.py:382)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight read AP, address: 00000000, data: 00000000 (11022ms since start, debug_probe_pyocd.py:190)
DEBUG:spsdk.dat.debug_mailbox:<- spin_write: 0x0001_0005 (11073ms since start, dm_commands.py:52)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight write AP, address: 00000004, data: 00010005 (11074ms since start, debug_probe_pyocd.py:220)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight read AP, address: 00000000, data: 00000000 (11077ms since start, debug_probe_pyocd.py:190)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight read AP, address: 00000008, data: 0001A5A5 (11111ms since start, debug_probe_pyocd.py:190)
DEBUG:spsdk.dat.debug_mailbox:-> spin_read:  0x0001_a5a5 (11111ms since start, dm_commands.py:61)
DEBUG:spsdk.dat.debug_mailbox:<- spin_write: 0x0000_0000 (11112ms since start, dm_commands.py:68)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight write AP, address: 00000004, data: 00000000 (11112ms since start, debug_probe_pyocd.py:220)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight read AP, address: 00000000, data: 00000000 (11116ms since start, debug_probe_pyocd.py:190)
DEBUG:spsdk.debuggers.debug_probe_pyocd:Coresight read AP, address: 00000008, data: 00000000 (11119ms since start, debug_probe_pyocd.py:190)
DEBUG:spsdk.dat.debug_mailbox:-> spin_read:  0x0000_0000 (11120ms since start, dm_commands.py:72)
DEBUG:pyocd.probe.pydapaccess.interface.pyusb_backend:closing interface
Entering into ISP mode succeeded

Some improvement, I guess. 🫤
In the "target was not halted as expected after calling flash algorithm routine (IPSR=3)" error, the IPSR=3 means that the core is in the HardFault handler. In other words, the flash algorithm crashed when it was called to init for . And unfortunately, NXP doesn't provide the source to the flash algorithms in their DFPs, so it's not possible to debug.

@flit Thanks for looking into this; looks like I'll have to look into using MCUBoot or similar.

@IvoBCD I've asked NXP for the source to the flash algorithm, seems it might be possible to get it.
There is also source to the .cfx algorithms included with the MCUXpresso IDE, located at <MCUXpresso IDE>/ide/Examples/Flashdrivers/NXP/iMXRT. While the .cfx doesn't appear to be compatible, it does have some of the same APIs as seen in the iMXRT6xxB_FlexSPI_SFDP/flashdriver/FlashPrg.c source file. I'm asking about how this is related to the CMSIS-Pack style .FLM algorithms used by pyocd.
Also… it turns out that I do actually have an MIMXRT685-EVK! (I have so many boards that it's sometimes hard to remember what I do and don't have.) Sorry I forgot about this and made you do all the testing yourself.

I am new to pyocd. I am trying to erase and program flash on NXP i.MX RT685 EVK using pyocd. Discussion on this thread helped me to overcome initial challenges and configure the pyocd_user.py script. Thanks !
I ran into the same issue described here.
0006956 C target was not halted as expected after calling flash algorithm routine (IPSR=3) [main]
Has anyone found a fix for this issue ?


fix: remove defunct sample explorer

SampleExplorer was removed in: https://github.com/pymmcore-plus/pymmcore-widgets/pull/139
need to also remove it here. Also seems as though some recent changes in useq have led to mypy issues

huh. locally I got these mypy errors, but not here it seems:
src/napari_micromanager/_saving.py:86: error: Argument 1 to "len" has
incompatible type
"Union[MultiPhaseTimePlan, TIntervalDuration, TIntervalLoops, TDurationLoops, None]";
expected "Sized"  [arg-type]
                    if len(sequence.time_plan) == 0
                           ^~~~~~~~~~~~~~~~~~
src/napari_micromanager/_saving.py:109: error: Argument 1 to "len" has
incompatible type
"Union[MultiPhaseTimePlan, TIntervalDuration, TIntervalLoops, TDurationLoops, None]";
expected "Sized"  [arg-type]
    ...      ax = sequence.axis_order.index("p") if len(sequence.time_plan) >...
                                                        ^~~~~~~~~~~~~~~~~~
Found 2 errors in 1 file (checked 1 source file)

I think merging this will allow https://github.com/pymmcore-plus/napari-micromanager/pull/258 to be merged also

huh. locally I got these mypy errors, but not here it seems:

yep, these are valid... looks like pre-commit is perhaps using a cached environment.  Will fix elsewhere


Created my linkfree Profile WaleyDevOps

Fixes Issue

Changes proposed

Check List (Check all the applicable boxes)

[x] My code follows the code style of this project.
[ ] My change requires changes to the documentation.
[ ] I have updated the documentation accordingly.
[ ] All new and existing tests passed.
[x] This PR does not contain plagiarized content.
[x] The title of my pull request is a short description of the requested changes.

Screenshots

Note to reviewers

@emmalearnscode , I have undo the changes as requested.


login only supports nsec keys

https://twitter.com/Printer_Gobrrr/status/1614875124087357440
Should be able to accept hex keys

https://twitter.com/qecez/status/1615120199195189248

fixed with https://github.com/neb-b/daisy/commit/83011a80241db632265da026244713668b3aff06


Shared folder inside blazor project should be placed inside the pages folder

The shared folder inside the blazor project should be placed in the pages folder.
Eg:
Pages > Shared
Pages > Admin > Products > Index.razor
Pages > Admin > Products > New.razor
Pages > Home > Index.razor
Since blazor is a mixture of c# and html there is no need for controllers to handle requests. You only need to define a service.
Folder structure for blazor will be:
Services > ProductSerivce.cs
Pages > ...
Let me know if you'll like me to create a sample of what I'm talking about.
Thank you!!!

@prince272 If your project gets bigger you'll notice that calling pages like Index or New is pretty annoying. Since a lot of features (like the products/customers/etc.) have these pages. I do recommend using the folders but still, prefix the page with the feature's name. Unless you want to import namespaces everywhere (which doesn't have decent support in VS at the moment).
e.g.
Product.Index.cs
Product.Create.cs
...

Yeah. You're right. A folder structure like that will do.

But my main question is, why did you move the shared folder from the pages folder. In razor application the shared folder was inside the pages folder.

Because the Layout page//Navmenu is not really a page?

Oh okay.

We can now close the comment.
When I first started web programming I asked myself that "where is C# events. Now thanks to blazor events with c# is back in the game".

Just calling @onClick welcomed c# events. Before we had to use JavaScript events.


Update docker go pkg

Desired Outcome
Update the github.com/docker/docker Go package to address vulnerabilities in the current version.
Connected Issue/Story
N/A
Changelog

[x] The CHANGELOG has been updated, or
[ ] This PR does not include user-facing changes and doesn't require a
CHANGELOG update

Test coverage

[ ] This PR includes new unit and integration tests to go with the code
changes, or
[x] The changes in this PR do not require tests

Documentation

[ ] Docs (e.g. READMEs) were updated in this PR
[ ] A follow-up issue to update official docs has been filed here: [insert issue ID]
[x] This PR does not require updating any documentation

Behavior

[ ] This PR changes product behavior and has been reviewed by a PO, or
[ ] These changes are part of a larger initiative that will be reviewed later, or
[x] No behavior was changed with this PR

Security

[x] Security architect has reviewed the changes in this PR,
[ ] These changes are part of a larger initiative with a separate security review, or
[ ] There are no security aspects to these changes

Moved to GH Enterprise


Reduce code redundancy through additional template in blocking_queue

Description
Thanks for your great work on this project,  solving one of the main painpoints for most robotics applications today with modern c++!
By skimming through it, I noticed that some code redundancy could be removed. However this comes at the cost of having to write the type of constructed object for the functions explicitly, as can be seen in the examples.
What do you think?
I am not sure how to mark this PR, since [Feat] is not really applicable in my opinion. Do you have conventions for refactorings?
Type of change

New feature (non-breaking change which adds functionality). Actually its a proposal for reducing redundancy, but this was the best fit of the options...

Checklist before requesting a review

[x] I have performed a self-review of my code.
[x] If it is a core feature, I have added thorough tests. -> tested it with the examples and tests supplied
[ ] If this is a new component I have added examples. -> not applicable
[ ] I updated the README and related documentation. -> not needed since functionality is the same

Ready for merge from my side. I think the ci-workflow needs approval from your side @filippobrizzi, correct?

Ready for merge from my side. I think the ci-workflow needs approval from your side @filippobrizzi, correct?

@johannes-graeter I merged the PR, thanks again for your contribution!


OSError: [Errno 101] Network is unreachable (CON-355)

Hi  espressif team:
I hv meet a problem when i run ./install.sh , log as fllow:

xxxx:~/Work/esp-matter$ ./install.sh

Running Matter Setup

  WELCOME TO...

         █
         █
     ▄   █   ▄                                █     █
     ▀▀█████▀▀      ▄▀▀▀▄ ▄▀▀▀▄    ▄▀▀▀▀▄█  ▀▀█▀▀▀▀▀█▀▀   ▄▀▀▀▀▄    ▄▀▀
   ▀█▄       ▄█▀   █     █     █  █      █    █     █    █▄▄▄▄▄▄█  █
     ▀█▄   ▄█▀     █     █     █  █      █    █     █    █         █
  ▄██▀▀█   █▀▀██▄  █     █     █   ▀▄▄▄▄▀█    ▀▄▄   ▀▄▄   ▀▄▄▄▄▀   █
 ▀▀    █   █    ▀▀

  BOOTSTRAP! Bootstrap may take a few minutes; please be patient.

Downloading and installing packages into local source directory:

  Setting up CIPD package manager...Traceback (most recent call last):
  File "/home/sid/Work/esp-matter/connectedhomeip/connectedhomeip/third_party/pigweed/repo/pw_env_setup/py/pw_env_setup/env_setup.py", line 795, in <module>
    sys.exit(main())
  File "/home/sid/Work/esp-matter/connectedhomeip/connectedhomeip/third_party/pigweed/repo/pw_env_setup/py/pw_env_setup/env_setup.py", line 787, in main
    return EnvSetup(**vars(parse())).setup()
  File "/home/sid/Work/esp-matter/connectedhomeip/connectedhomeip/third_party/pigweed/repo/pw_env_setup/py/pw_env_setup/env_setup.py", line 457, in setup
    result = step(spin)
  File "/home/sid/Work/esp-matter/connectedhomeip/connectedhomeip/third_party/pigweed/repo/pw_env_setup/py/pw_env_setup/env_setup.py", line 546, in cipd
    cipd_client = cipd_wrapper.init(
  File "/home/sid/Work/esp-matter/connectedhomeip/connectedhomeip/third_party/pigweed/repo/pw_env_setup/py/pw_env_setup/cipd_setup/wrapper.py", line 357, in init
    bootstrap(client, silent, rosetta=rosetta)
  File "/home/sid/Work/esp-matter/connectedhomeip/connectedhomeip/third_party/pigweed/repo/pw_env_setup/py/pw_env_setup/cipd_setup/wrapper.py", line 311, in bootstrap
    tmp.write(client_bytes(rosetta))
  File "/home/sid/Work/esp-matter/connectedhomeip/connectedhomeip/third_party/pigweed/repo/pw_env_setup/py/pw_env_setup/cipd_setup/wrapper.py", line 240, in client_bytes
    conn.request('GET', path)
  File "/usr/lib/python3.8/http/client.py", line 1256, in request
    self._send_request(method, url, body, headers, encode_chunked)
  File "/usr/lib/python3.8/http/client.py", line 1302, in _send_request
    self.endheaders(body, encode_chunked=encode_chunked)
  File "/usr/lib/python3.8/http/client.py", line 1251, in endheaders
    self._send_output(message_body, encode_chunked=encode_chunked)
  File "/usr/lib/python3.8/http/client.py", line 1011, in _send_output
    self.send(msg)
  File "/usr/lib/python3.8/http/client.py", line 951, in send
    self.connect()
  File "/usr/lib/python3.8/http/client.py", line 1418, in connect
    super().connect()
  File "/usr/lib/python3.8/http/client.py", line 922, in connect
    self.sock = self._create_connection(
  File "/usr/lib/python3.8/socket.py", line 808, in create_connection
    raise err
  File "/usr/lib/python3.8/socket.py", line 796, in create_connection
    sock.connect(sa)
OSError: [Errno 101] Network is unreachable

the Prerequisites for Matter and espif (4.4.2) is ready.
and i found that issue(https://github.com/project-chip/connectedhomeip/issues/2893) had beed fixed
ping www.google.com is ok

~/Work/esp-matter$ ping www.google.com
PING www.google.com (<IP_ADDRESS>) 56(84) bytes of data.
64 bytes from hkg07s38-in-f4.1e100.net (<IP_ADDRESS>): icmp_seq=1 ttl=128 time=7.73 ms
64 bytes from hkg07s38-in-f4.1e100.net (<IP_ADDRESS>): icmp_seq=2 ttl=128 time=6.96 ms
64 bytes from hkg07s38-in-f4.1e100.net (<IP_ADDRESS>): icmp_seq=3 ttl=128 time=6.79 ms
64 bytes from hkg07s38-in-f4.1e100.net (<IP_ADDRESS>): icmp_seq=4 ttl=128 time=6.63 ms

hope you give me some advise, thank you

@sidhoo-root  This seems to be an issue with the upstream connectedhomeip repo. Can you please check: https://github.com/project-chip/connectedhomeip/issues/8810

@dhrishi ok ,thanks. and Is it related to using a virtual machine environment to install ?

@sidhoo-root Yes, it seems so

@dhrishi i had installed it on the Ubuntu machine, it still report this error.   and the host : chrome-infra-packages.appspot.com can be ping, does it means the CIPD_HOST = 'chrome-infra-packages.appspot.com'  works in  my env ?

PING chrome-infra-packages.appspot.com (<IP_ADDRESS>) 56(84) bytes of data.
64 bytes from 199-193-116-105.static.hvvc.us (<IP_ADDRESS>): icmp_seq=1 ttl=128 time=220 ms
64 bytes from 199-193-116-105.static.hvvc.us (<IP_ADDRESS>): icmp_seq=2 ttl=128 time=218 ms
64 bytes from 199-193-116-105.static.hvvc.us (<IP_ADDRESS>): icmp_seq=3 ttl=128 time=219 ms
64 bytes from 199-193-116-105.static.hvvc.us (<IP_ADDRESS>): icmp_seq=4 ttl=128 time=220 ms
64 bytes from 199-193-116-105.static.hvvc.us (<IP_ADDRESS>): icmp_seq=5 ttl=128 time=218 ms

@dhrishi the problem was solved,  because the dns can't be parsed correctly in my office network

@sidhoo-root Good to know that the issue is identified and resolved.

我也遇到这个问题了，使用虚拟机vmware15.0  ubuntu 22.10系统，已经翻墙了，但是依然会报这个错误，有没有解决办法？

@dhrishi问题解决了，因为在我的办公网络中dns无法正确解析

您好，想问一下是如何解决的，我也遇到了这个问题，ping youtube 跟google都没有问题

@dhrishi问题解决了，因为在我的办公网络中dns无法正确解决

您好，想问下是如何解决的，我也遇到了这个问题，ping youtube跟google都没有问题

泪目了~终于搞定了，我就说怎么Ubuntu里面明明都可以访问外网，但是就是一直提示我有问题，不应该的啊，然后在命令行里面定义了一下IP就行了

@dhrishi问题解决了，因为在我的办公网络中dns无法正确解决

您好，想问下是如何解决的，我也遇到了这个问题，ping youtube跟google都没有问题

 泪目了~终于搞定了，我就说怎么Ubuntu里面明明都可以访问外网，但是就是一直提示我有问题，不应该的啊，然后在命令行里面定义了一下IP就行了

Same issue,Could you please explain  how to '命令行里面定义了一下IP'?Thanx!

@dhrishi问题解决了，因为在我的办公网络中dns无法正确解决

您好，想问下是如何解决的，我也遇到了这个问题，ping youtube跟google都没有问题

 泪目了~终于搞定了，我就说怎么Ubuntu里面明明都可以访问外网，但是就是一直提示我有问题，不应该的啊，然后在命令行里面定义了一下IP就行了

Same issue,Could you please explain how to '命令行里面定义了一下IP'?Thanx!

sure，u can open the sofeware and the click here just as show in the picture as below.

copy that in terminal command line it will connect normally.

@dhrishi问题解决了，因为在我的办公网络中dns无法正确解决

您好，想问下是如何解决的，我也遇到了这个问题，ping youtube跟google都没有问题

 泪目了~终于搞定了，我就说怎么Ubuntu里面明明都可以访问外网，但是就是一直提示我有问题，不应该的啊，然后在命令行里面定义了一下IP就行了

Same issue,Could you please explain how to '命令行里面定义了一下IP'?Thanx!

sure，u can open the sofeware and the click here just as show in the picture as below.   copy that in terminal command line it will connect normally.

Thanx for your reply!I will take a try.


No tooltip on some User accounts buttons

Hello
I was running the dev version of IPT (2.6.4 snapshot) and I noticed all the new graphical improvements !!! well done !!!
Just a remark on the User Account page.
I can see a tooltip on "delete user" button, but not on Edit and Reset Password.

Thank you very much I appreciate that.
Indeed, those don't have a title property, I'll fix that in the next version


provide list of all previously merged ncRNA

A these will be RNA  features with a

systmetic IDs which is a synonym of another extant feature.

B @kimrutherford  you also mentioned just finding all of the overlapping ncRNAs (on the same strand). this is a good idea.
A should be a subset of B anyway...

@kimrutherford you also mentioned just finding all of the overlapping ncRNAs (on the same strand). this is a good idea.

I've done some querying and get 117 cases of overlapping RNAs.  An RNA will appear more than once in the table if it overlaps more than one other RNA (eg. SPNCRNA.1208).  Let me know if you'd like this table in a different format.
     rna      | overlapping_rna
--------------+-----------------
 SPNCRNA.605  | SPNCRNA.139
 SPSNORNA.49  | SPNCRNA.617
 SPNCRNA.626  | SPNCRNA.03
 SPNCRNA.551  | SPNCRNA.653
 SPNCRNA.656  | SPNCRNA.655
 SPSNORNA.02  | SPNCRNA.659
 SPSNORNA.03  | SPNCRNA.659
 SPSNORNA.04  | SPNCRNA.659
 SPSNORNA.05  | SPNCRNA.659
 SPSNORNA.06  | SPNCRNA.659
 SPNCRNA.79   | SPNCRNA.672
 SPNCRNA.712  | SPNCRNA.711
 SPSNORNA.07  | SPNCRNA.723
 SPSNORNA.08  | SPNCRNA.723
 SPSNORNA.09  | SPNCRNA.723
 SPNCRNA.86   | SPNCRNA.736
 SPNCRNA.557  | SPNCRNA.772
 SPSNORNA.50  | SPNCRNA.814
 SPNCRNA.192  | SPNCRNA.818
 SPNCRNA.831  | SPNCRNA.197
 SPNCRNA.836  | SPNCRNA.835
 SPNCRNA.205  | SPNCRNA.848
 SPNCRNA.858  | SPNCRNA.559
 SPNCRNA.528  | SPNCRNA.860
 SPNCRNA.210  | SPNCRNA.865
 SPNCRNA.31   | SPNCRNA.867
 SPNCRNA.873  | SPNCRNA.872
 SPNCRNA.882  | SPNCRNA.212
 SPNCRNA.219  | SPNCRNA.893
 SPSNORNA.43  | SPNCRNA.901
 SPNCRNA.529  | SPNCRNA.911
 SPNCRNA.913  | SPNCRNA.912
 SPNCRNA.236  | SPNCRNA.941
 SPNCRNA.985  | SPNCRNA.246
 SPNCRNA.996  | SPNCRNA.248
 SPNCRNA.563  | SPNCRNA.998
 SPNCRNA.1011 | SPNCRNA.1010
 SPNCRNA.1031 | SPNCRNA.1030
 SPNCRNA.1032 | SPNCRNA.254
 SPNCRNA.564  | SPNCRNA.1036
 SPNCRNA.1037 | SPNCRNA.564
 SPNCRNA.256  | SPNCRNA.1039
 SPNCRNA.1083 | SPNCRNA.1082
 SPNCRNA.30   | SPNCRNA.1087
 SPNCRNA.277  | SPNCRNA.1089
 SPNCRNA.4477 | SPNCRNA.1705
 SPNCRNA.4478 | SPNCRNA.1705
 SPNCRNA.1703 | SPNCRNA.4496
 SPNCRNA.4499 | SPNCRNA.1704
 SPNCRNA.299  | SPNCRNA.1333
 SPNCRNA.1352 | SPNCRNA.1351
 SPNCRNA.534  | SPNCRNA.1362
 SPNCRNA.1371 | SPNCRNA.1370
 SPNCRNA.321  | SPNCRNA.1379
 SPNCRNA.329  | SPNCRNA.1387
 SPSNORNA.35  | SPNCRNA.1394
 SPNCRNA.332  | SPNCRNA.1395
 SPNCRNA.566  | SPNCRNA.1397
 SPNCRNA.335  | SPNCRNA.1399
 SPNCRNA.338  | SPNCRNA.1411
 SPSNORNA.47  | SPNCRNA.1436
 SPNCRNA.358  | SPNCRNA.1448
 SPNCRNA.17   | SPNCRNA.1463
 SPNCRNA.571  | SPNCRNA.1481
 SPSNORNA.25  | SPNCRNA.1483
 SPNCRNA.1493 | SPNCRNA.38
 SPNCRNA.1502 | SPBTRNAPRO.06
 SPNCRNA.398  | SPNCRNA.1520
 SPNCRNA.539  | SPNCRNA.1533
 SPNCRNA.1707 | SPNCRNA.5748
 SPNCRNA.1548 | SPNCRNA.1547
 SPNCRNA.26   | SPNCRNA.1553
 SPNCRNA.1575 | SPNCRNA.1574
 SPNCRNA.23   | SPNCRNA.1580
 SPNCRNA.541  | SPNCRNA.1582
 SPSNORNA.33  | SPNCRNA.1597
 SPNCRNA.1598 | SPNCRNA.419
 SPNCRNA.1599 | SPNCRNA.419
 SPNCRNA.1608 | SPNCRNA.574
 SPNCRNA.424  | SPNCRNA.1619
 SPNCRNA.426  | SPNCRNA.1624
 SPNCRNA.20   | SPNCRNA.1649
 SPSNORNA.28  | SPNCRNA.1650
 SPNCRNA.1657 | SPNCRNA.436
 SPNCRNA.1659 | SPNCRNA.1658
 SPNCRNA.1664 | SPNCRNA.1663
 SPNCRNA.1674 | SPNCRNA.1672
 SPNCRNA.113  | SPNCRNA.1674
 SPNCRNA.1691 | SPNCRNA.1690
 SPNCRNA.444  | SPNCRNA.1693
 SPNCRNA.532  | SPNCRNA.1696
 SPNCRNA.1100 | SPNCRNA.1099
 SPNCRNA.455  | SPNCRNA.1111
 SPNCRNA.458  | SPNCRNA.1115
 SPNCRNA.578  | SPNCRNA.1132
 SPNCRNA.1136 | SPNCRNA.579
 SPNCRNA.1137 | SPNCRNA.02
 SPNCRNA.1158 | SPNCRNA.1157
 SPNCRNA.7117 | SPNCRNA.1706
 SPNCRNA.478  | SPNCRNA.1163
 SPNCRNA.491  | SPNCRNA.1189
 SPNCRNA.132  | SPNCRNA.1203
 SPNCRNA.69   | SPNCRNA.1203
 SPNCRNA.131  | SPNCRNA.1203
 SPNCRNA.69   | SPNCRNA.132
 SPNCRNA.131  | SPNCRNA.69
 SPNCRNA.582  | SPNCRNA.1207
 SPNCRNA.1208 | SPNCRNA.1207
 SPNCRNA.1208 | SPNCRNA.582
 SPNCRNA.1217 | SPNCRNA.583
 SPSNORNA.41  | SPNCRNA.7474
 SPNCRNA.501  | SPNCRNA.1226
 SPNCRNA.1235 | SPNCRNA.504
 SPNCRNA.1238 | SPNCRNA.1237
 SPNCRNA.1240 | SPNCRNA.1239
 SPNCRNA.123  | SPNCRNA.1269
 SPNCRNA.523  | SPNCRNA.1293

Note to self:
CREATE TABLE featurelocrange (feature_id integer not null unique, range int4range not null, srcfeature_id integer, strand smallint);

ALTER TABLE ONLY featurelocrange
    ADD CONSTRAINT featureloc_feature_id_fkey
       FOREIGN KEY (feature_id)
        REFERENCES feature(feature_id) ON DELETE CASCADE DEFERRABLE INITIALLY DEFERRED;

ALTER TABLE ONLY featurelocrange
    ADD CONSTRAINT featureloc_srcfeature_id_fkey
       FOREIGN KEY (srcfeature_id)
        REFERENCES feature(feature_id) ON DELETE CASCADE DEFERRABLE INITIALLY DEFERRED;

CREATE INDEX featurelocrange_idx ON featurelocrange USING GIST (range);

INSERT INTO featurelocrange(feature_id, range, srcfeature_id, strand)
     SELECT feature_id, int4range(fmin+1, fmax), srcfeature_id, strand
       FROM featureloc;

CREATE TABLE rna_gene_features AS
  (SELECT gene.feature_id
   FROM feature gene
   JOIN cvterm g_type ON g_type.cvterm_id = gene.type_id
   JOIN featu re_relationship rel ON rel.object_id = gene.feature_id
   JOIN feature transcript ON transcript.feature_id = rel.subject_id
   JOIN cvterm t_type ON transcript.type_id = t_t ype.cvterm_id
   WHERE t_type.name like '%RNA%'
     AND t_type.name <> 'mRNA'
     AND g_type.name = 'gene'
     AND gene.organism_id in
       (SELECT organism_id
        FROM organism
        WHERE abbrevi ation = 'Spombe')
     AND transcript.organism_id in
       (SELECT organism_id
        FROM organism
        WHERE abbreviation = 'Spombe'));

CREATE INDEX rna_gene_features_idx ON rna_gene_features(feature_id);

SELECT r1feature.uniquename AS rna,
       r2feature.uniquename AS overlapping_rna
FROM rna_gene_features r1
JOIN feature r1feature ON r1.feature_id = r1feature.feature_id
JOIN featurelocrange r1range ON r1.feature_id = r1range.feature_id,
                                rna_gene_features r2
JOIN feature r2feature ON r2.feature_id = r2feature.feature_id
JOIN featurelocrange r2range ON r2.feature_id = r2range.feature_id
WHERE r1.feature_id <> r2.feature_id
  AND r1range.strand = r2range.strand
  AND r1range.srcfeature_id = r2range.srcfeature_id
  AND r1range.range && r2range.range
  AND r1.feature_id > r2.feature_id;

Now I've got SQL I can copy and paste to do other overlap queries in case they're ever needed.
For example:

RNA genes that overlap protein coding genes on the same strand
intergenic RNAs
antisense RNAs

These are the merges from the above list:
SPNCRNA.551  | SPNCRNA.653. MERGED
SPNCRNA.557  | SPNCRNA.772 MERGED
SPNCRNA.831  | SPNCRNA.197 MERGED
SPNCRNA.205  | SPNCRNA.848 MERGED
SPNCRNA.858  | SPNCRNA.559 MERGED
SPNCRNA.210  | SPNCRNA.865 MERGED
SPNCRNA.882  | SPNCRNA.212 MERGED
SPNCRNA.236  | SPNCRNA.941 MERGED
SPNCRNA.985  | SPNCRNA.246 MERGED
SPNCRNA.1032 | SPNCRNA.254 MERGED
SPNCRNA.1037 | SPNCRNA.564 MERGED
SPNCRNA.1703 | SPNCRNA.4496 MERGED
SPNCRNA.4499 | SPNCRNA.1704 MERGED
SPNCRNA.299  | SPNCRNA.1333 MERGED
SPNCRNA.321  | SPNCRNA.1379 MERGED
SPNCRNA.329  | SPNCRNA.1387 MERGED
SPSNORNA.47  | SPNCRNA.1436 RE_MERGED
SPNCRNA.1493 | SPNCRNA.38 MERGED
SPNCRNA.539  | SPNCRNA.1533 MERGED
SPNCRNA.1707 | SPNCRNA.5748 MERGED
SPNCRNA.541  | SPNCRNA.1582 MERGED
SPNCRNA.1598 | SPNCRNA.419 MERGED
SPNCRNA.424  | SPNCRNA.1619 MERGED
SPNCRNA.426  | SPNCRNA.1624 MERGED
SPNCRNA.20   | SPNCRNA.1649 MERGED
SPNCRNA.1657 | SPNCRNA.436  MERGED
SPNCRNA.113  | SPNCRNA.1674 MERGED gene structure updated to SPNCRNA.113
SPNCRNA.458  | SPNCRNA.1115 MERGED
SPNCRNA.578  | SPNCRNA.1132 MERGED
SPNCRNA.7117 | SPNCRNA.1706 MERGED
SPNCRNA.478  | SPNCRNA.1163 MERGED
SPNCRNA.582  | SPNCRNA.1207 REMERGED
SPNCRNA.1217 | SPNCRNA.583 MERGED
SPNCRNA.1235 | SPNCRNA.504 MERGED
SPNCRNA.523  | SPNCRNA.1293 MERGED\
@manulera

Here's an updated list of the remaining overlapping RNAs.
I had the issue still open in a tab so I thought I'd run the SQL again.  If you need it, we could put this in a nightly log file.
     rna      | overlapping_rna
--------------+-----------------
 SPNCRNA.626  | SPNCRNA.03
 SPNCRNA.79   | SPNCRNA.672
 SPNCRNA.712  | SPNCRNA.711
 SPNCRNA.86   | SPNCRNA.736
 SPSNORNA.50  | SPNCRNA.814
 SPNCRNA.836  | SPNCRNA.835
 SPNCRNA.31   | SPNCRNA.867
 SPSNORNA.43  | SPNCRNA.901
 SPNCRNA.1011 | SPNCRNA.1010
 SPNCRNA.1031 | SPNCRNA.1030
 SPNCRNA.1371 | SPNCRNA.1370
 SPNCRNA.338  | SPNCRNA.1411
 SPNCRNA.358  | SPNCRNA.1448
 SPSNORNA.25  | SPNCRNA.1483
 SPNCRNA.1493 | SPNCRNA.38
 SPNCRNA.1548 | SPNCRNA.1547
 SPNCRNA.23   | SPNCRNA.1580
 SPSNORNA.28  | SPNCRNA.1650
 SPNCRNA.1136 | SPNCRNA.579
 SPNCRNA.1137 | SPNCRNA.02
 SPNCRNA.491  | SPNCRNA.1189
 SPNCRNA.1238 | SPNCRNA.1237
 SPNCRNA.1240 | SPNCRNA.1239
 SPNCRNA.123  | SPNCRNA.1269
 SPSNORNA.49  | SPNCRNA.617
 SPSNORNA.02  | SPNCRNA.659
 SPSNORNA.03  | SPNCRNA.659
 SPSNORNA.04  | SPNCRNA.659
 SPSNORNA.05  | SPNCRNA.659
 SPSNORNA.06  | SPNCRNA.659
 SPSNORNA.07  | SPNCRNA.723
 SPSNORNA.08  | SPNCRNA.723
 SPSNORNA.09  | SPNCRNA.723
 SPNCRNA.873  | SPNCRNA.872
 SPNCRNA.913  | SPNCRNA.912
 SPNCRNA.563  | SPNCRNA.998
 SPNCRNA.1083 | SPNCRNA.1082
 SPNCRNA.534  | SPNCRNA.1362
 SPNCRNA.398  | SPNCRNA.1520
 SPNCRNA.1664 | SPNCRNA.1663
 SPNCRNA.1100 | SPNCRNA.1099
 SPNCRNA.455  | SPNCRNA.1111
 SPNCRNA.132  | SPNCRNA.1203
 SPNCRNA.69   | SPNCRNA.132
 SPNCRNA.69   | SPNCRNA.1203
 SPNCRNA.131  | SPNCRNA.69
 SPNCRNA.131  | SPNCRNA.1203
 SPNCRNA.1208 | SPNCRNA.1207
 SPNCRNA.605  | SPNCRNA.139
 SPNCRNA.656  | SPNCRNA.655
 SPNCRNA.192  | SPNCRNA.818
 SPNCRNA.256  | SPNCRNA.1039
 SPNCRNA.30   | SPNCRNA.1087
 SPNCRNA.4477 | SPNCRNA.1705
 SPNCRNA.4478 | SPNCRNA.1705
 SPNCRNA.1352 | SPNCRNA.1351
 SPSNORNA.35  | SPNCRNA.1394
 SPNCRNA.332  | SPNCRNA.1395
 SPNCRNA.566  | SPNCRNA.1397
 SPNCRNA.335  | SPNCRNA.1399
 SPNCRNA.17   | SPNCRNA.1463
 SPNCRNA.26   | SPNCRNA.1553
 SPNCRNA.1575 | SPNCRNA.1574
 SPNCRNA.1659 | SPNCRNA.1658
 SPNCRNA.1691 | SPNCRNA.1690
 SPNCRNA.1158 | SPNCRNA.1157
 SPSNORNA.41  | SPNCRNA.7474
 SPNCRNA.501  | SPNCRNA.1226

Some are overlapping, but cannot be merged because they don't fully overlap, e.g.

I think I already checked them all and merged those which were almost entirely coincident so I'll close this one.


ValueError: file_type not specified!

Hi,
When I run sim_grasp_multiple.py and add the parameter --vis for simulation grasping, the following problem occurred:
(giga) wang@wang-U:~/github/GIGA$  python scripts/sim_grasp_multiple.py --num-view 1 --object-set pile/test --scene pile --num-rounds 100 --sideview --add-noise dex --force --best --model /home/wang/github/GIGA/data/models/giga_pile.pt --type giga --result-path /home/wang/github/GIGA/data/result --vis
pybullet build time: May 28 2020 16:37:34
Loading [giga] model from /home/wang/github/GIGA/data/models/giga_pile.pt
0%|                                                                                | 0/100 [00:00<?, ?it/s]
Traceback (most recent call last):
File "scripts/sim_grasp_multiple.py", line 123, in
main(args)
File "scripts/sim_grasp_multiple.py", line 38, in main
success_rate, declutter_rate = clutter_removal.run(
File "/home/wang/github/GIGA/src/vgn/experiments/clutter_removal.py", line 89, in run
logger.log_mesh(scene_mesh, visual_mesh, f'round_{round_id:03d}trial{trial_id:03d}')
File "/home/wang/github/GIGA/src/vgn/experiments/clutter_removal.py", line 177, in log_mesh
aff_mesh.export(self.mesh_dir / (name + "_aff.obj"))
File "/home/wang/anaconda3/envs/giga/lib/python3.8/site-packages/trimesh/scene/scene.py", line 842, in export
return export.export_scene(
File "/home/wang/anaconda3/envs/giga/lib/python3.8/site-packages/trimesh/exchange/export.py", line 210, in export_scene
raise ValueError('file_type not specified!')
ValueError: file_type not specified!
What is the reason?
Thank you！ ^_^

I update trimesh to the latest version and it still doesn’t work, and I print out the path of self.mesh_dir / (name + "_aff.obj"),is PosixPath(‘data/experiments/21-08-13-20-33-46/meshes/round_000_trial_000_aff.obj') .How to specify the file_type='obj' ?

You can try aff_mesh.export(self.mesh_dir / (name + "_aff.obj"), file_type='obj'). If this still does not work, actually the visualization is not necessary for running, and you can remove the argument --vis.

I update trimesh to the latest version and it still doesn’t work, and I print out the path of self.mesh_dir / (name + "_aff.obj"),is PosixPath(‘data/experiments/21-08-13-20-33-46/meshes/round_000_trial_000_aff.obj') .How to specify the file_type='obj' ?

Hi，
excuse me, have you realized the function of visualization?

I update trimesh to the latest version and it still doesn’t work, and I print out the path of self.mesh_dir / (name + "_aff.obj"),is PosixPath(‘data/experiments/21-08-13-20-33-46/meshes/round_000_trial_000_aff.obj') .How to specify the file_type='obj' ?

Hi，
excuse me, have you realized the function of visualization?

Not yet, how about you?

You can try aff_mesh.export(self.mesh_dir / (name + "_aff.obj"), file_type='obj'). If this still does not work, actually the visualization is not necessary for running, and you can remove the argument --vis.

Excuse me, I want to achieve the visualization results (Visualization of the grasp affordance landscape and predicted grasps) in your paper.  Does the code you upload have this function?

I update trimesh to the latest version and it still doesn’t work, and I print out the path of self.mesh_dir / (name + "_aff.obj"),is PosixPath(‘data/experiments/21-08-13-20-33-46/meshes/round_000_trial_000_aff.obj') .How to specify the file_type='obj' ?

Hi，
excuse me, have you realized the function of visualization?

Not yet, how about you?

not yet

You can try aff_mesh.export(self.mesh_dir / (name + "_aff.obj"), file_type='obj'). If this still does not work, actually the visualization is not necessary for running, and you can remove the argument --vis.

Excuse me, I want to achieve the visualization results (Visualization of the grasp affordance landscape and predicted grasps) in your paper. Does the code you upload have this function?

Yes, the code will save the visualization to obj file if you use the argument --vis. However, I don't know why you meet error when running aff_mesh.export.

I tried aff_mesh.export(str(self.mesh_dir / (name + "_aff.obj"))), the issue of file_type disappeared.
Then i appeared array out of bounds (IndexError: index 201 is out of bounds for axis 0 with size 201).
Finally, found that the data of data/urdfs/packed/test/Paprika_800_tex_visual.obj is short of the letter 'v'(at the line of 15).

I tried aff_mesh.export(str(self.mesh_dir / (name + "_aff.obj"))), the issue of file_type disappeared.
Then i appeared the issue of array out of bounds (IndexError: index 201 is out of bounds for axis 0 with size 201).
Finally, found that the data of data/urdfs/packed/test/Paprika_800_tex_visual.obj is short of the letter 'v'(at the line of 15).

Hmm, that's interesting. Because I checked the data that I uploaded, and there's no such problem.

I tried aff_mesh.export(str(self.mesh_dir / (name + "_aff.obj"))), the issue of file_type disappeared.
Then i appeared the issue of array out of bounds (IndexError: index 201 is out of bounds for axis 0 with size 201).
Finally, found that the data of data/urdfs/packed/test/Paprika_800_tex_visual.obj is short of the letter 'v'(at the line of 15).

Hmm, that's interesting. Because I checked the data that I uploaded, and there's no such problem.

I just re-extracted the data.zip file and found that the data is complete.
I want to know how long have you cost about training vgn one epoch. I performed on a computer with a GTX 1080 Ti graphics card and  the memory is 32G, but my cpu is noot good. I cost about 14 hours one epoch. I want to know if it’s the cpu problem.

I tried aff_mesh.export(str(self.mesh_dir / (name + "_aff.obj"))), the issue of file_type disappeared.
Then i appeared the issue of array out of bounds (IndexError: index 201 is out of bounds for axis 0 with size 201).
Finally, found that the data of data/urdfs/packed/test/Paprika_800_tex_visual.obj is short of the letter 'v'(at the line of 15).

Hmm, that's interesting. Because I checked the data that I uploaded, and there's no such problem.

I just re-extracted the data.zip file and found that the data is complete.
I want to know how long have you cost about training vgn one epoch. I performed on a computer with a GTX 1080 Ti graphics card and the memory is 32G, but my cpu is noot good. I cost about 14 hours one epoch. I want to know if it’s the cpu problem.

When training the network on pile dataset (the larger one), one epoch takes 2 hours on one RTX 2080 Ti. So I think the problem is with CPU. You can check the "Volatile GPU-Util" given by nvidia-smi to see if the GPU is fully used. GPU-Util over 80% is a good sign.

I tried aff_mesh.export(str(self.mesh_dir / (name + "_aff.obj"))), the issue of file_type disappeared.
Then i appeared the issue of array out of bounds (IndexError: index 201 is out of bounds for axis 0 with size 201).
Finally, found that the data of data/urdfs/packed/test/Paprika_800_tex_visual.obj is short of the letter 'v'(at the line of 15).

Hmm, that's interesting. Because I checked the data that I uploaded, and there's no such problem.

I just re-extracted the data.zip file and found that the data is complete.
I want to know how long have you cost about training vgn one epoch. I performed on a computer with a GTX 1080 Ti graphics card and the memory is 32G, but my cpu is noot good. I cost about 14 hours one epoch. I want to know if it’s the cpu problem.

Hi,I also encountered the problem of slow training, I suspect that the slow IO speed of the mechanical hard drive is the reason, have you solved this problem?