Add Master<->Slave SPI test

This patchset:

Fixes the spi_ll_stm32 Slave frame shifting to avoid leaving the transaction with bytes in the TX FIFO
Adds a new Master<->Slave SPI test using a physical on-board/header loopback with the SPI Slave controller in async mode while the Master controller acts in Sync mode.

I know @tbursztyka is working on a proper Slave API, but here its not incompatible since the test uses the transceive() call directly, and could be updated later on.
This patchset need #5199 to be tested

@tbursztyka could you have a look at the test ?

Fine by me, I see no problem with that test. slave does work that way, it's the API not addressing the issue when the slave protocol is more complicated (i.e. reacting at first byte reception, getting awake at slave select, etc... ) which is limiting here.

@mbolivar Is the Kconfig addition to the test ok for you ?

recheck

Shippable error says:
Warning: Could not extract kernel version

Not sure what is going on. Does it need a rebase or something?

The shippable failure "Warning: Could not extract kernel version" is coming from a step in the documentation build process that's trying to extract the kernel version information from the VERSION file (within the doc/conf.py configuration file) and is failing. @nashif merged a patch (#5329) for this in the master branch, but it has not been applied to the arm branch.

Looks like the doc build issues are resolved.  Great.

@galak what is the status of the PR ? will it be merged ?

I'll rebase against #5921 when merged.

@superna9999 While investigating SPI slave API (as seen in #5921) I had issues with designware driver, with a bit more complex samples (one that tries to use the slave input event): the slave gets out of sync. I thought I was missing something on designware side to I tested your patch made on stm32.  And the exact behaviour happens.
The difference with your sample here, besides using the SPI input event, is that I do my tests on 2 different boards: one acting as a master and one as a slave. Because on same board you get the possibility to trick the irq priorities so that slave gets a higher priority than the master, as you did, so that the slave is never "late" in reading the input data.
Actually I start to believe that it might not be exactly feasible to do what I want: slave being extremely dependent on host cpu and input event cb code, there is no way to guaranty that the slave will be answering on time to the master since the master drives the spi bus clock: so it might be on time, but it might also be too late in reading bytes from master and replying by writing to it. On designware, at best I get 1 byte out of sync, on stm32 I get 2 bytes. (With full debug, it of course gets really worse).
Check https://github.com/tbursztyka/zephyr/commits/spi_slave_wip
Maybe it's not worth trying to support "complex" slave protocols, and that we should just go with symmetrical transceive call from the start (so without any break in the transaction process: master and slave would have exact same length of buffers from the start). I might be missing something here.

Hi @tbursztyka
I had a hard time imaginating a way to handle the callbacks you implemented without a well defined Host behavior. Unlike I2C, SPI needs the host to leave setup/hold time after the CS and leave dummy bytes in the transaction, the problem is : how do enforce this ? We can't.... I think your code is ok, but you may add a big fat warning about the Host behaviour. The NOR Flash protocol needs a long setup and hold time, and some dummy bytes for some commands, for the same reasons. This is why we should support the symmetrical transceive calls as the default Slave interface with these optional calls if necessary.

Yep looks like I was banging my head on a non-solvable issue. That I think I'll drop the input stuff, and just have the normal spi_transceive() that could be used for slave as usual. Well, it's much easier then!
Thanks

@carlescufi yes, at least the fix in the stm32 spi driver to fix slave mode

Codecov Report

Merging #5200 into master will increase coverage by <.01%.
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@@            Coverage Diff             @@
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==========================================
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==========================================
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+ Misses      19208    19207       -1
  Partials     3913     3913

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@superna9999 hum, check spi.h, there was a big update ~2 months ago. dev is back as a parameter before config, and spi_buf are not directly passed, but instead go through spi_buf_set  in order to remove the length parameters.

@superna9999 @tbursztyka
I'm using this PR and seems to work fine. Nevertheless I put another fix which I think you need to take a look at: PR #7687
Moreover I had to decrease the SPI master speed at 500000, otherwise it was going in OVR error.
I'm investigating about the possibility to add DMA to STM32 SPI. Any plan yet?

Ah, in this PR I'm using this commit only: 7f07c8a

@avisconti On which SoC ? you should be able to receive at more than 500KHz on L4 and even F0
There is no plan to add DMA, but feel free to add it, it will be welcome !
I think I'll drop the second patch and repost the first patch in a separate PR, what do you think @tbursztyka ?

@superna9999 sure, the stm32 fix could be applied asap.


MINOR: Add Replication Quotas Test Rig

This test rig lives in the other.kafka package so isn't part of our standard tests. It provides a convenient mechanism for measuring throttling performance over time. Measurements for each experiment are charted and presented to the user in an html file. The output looks like this:
Experiment4

BrokerCount: 25
PartitionCount: 100
Throttle: 4,000,000 B/s
MsgCount: 1,000
MsgSize: 100,000
TargetBytesPerBrokerMB: 400

@ijuma @ewencp be good to make some progress on this PR too if you have a second.

@benstopford, sorry for the delay. I hope to have a chance spend some time on this on Monday (if Ewen doesn't beat me to it).

Cool - thanks :)

The dependency thing was my only comment -- even if there are follow ups, it's all super low risk since this is almost all in the test rig. Thanks @benstopford, LGTM!


add licensify environment hiera for aws integration

Context
For the licensify testing in AWS integration, there is a need for licensify bucket environment hiera for aws integration because otherwise, the licensify apps in integration do not have the full path of the AWS s3 bucket to store the application.
Decisions

set the relevant hiera

good idea but it is like that for staging and production, will have to go and change that to maintain consistency.


ChangeLog properties interpolation in sql file not working

Hi,
I have 2 levels of hierarchy in my changelogs as shown below and I need to define a property in the second level to be used in the included SQL files.
Expectation :
When I define the property in two changelog files at the second level the SQL files included in each changelog gets the value from the changelog
Actual behavior:
The variables are getting replaced in the sql file
I tried to define the property as local (global: false) but this didn't work as well.
Directory structure:

schema.yml
scripts

feat1

changelog.yml
change1.sql

feat2

changelog.yml
change2-1.sql

schema.yml:
databaseChangeLog:
  - include:
      file: scripts/feat1/changelog.yml
  - include:
      file: scripts/feat2/changelog.yml

scripts/feat1/changelog.yml:
databaseChangeLog:
  - property:
      name: MyProp
      value: feat1

  - include:
      file: change1.sql
      relativeToChangelogFile: true

scripts/feat2/changelog.yml:
databaseChangeLog:
  - property:
      name: MyProp
      value: feat2

  - include:
      file: change2-1.sql
      relativeToChangelogFile: true

scripts/feat1/change1.sql:
--liquibase formatted sql

--changeset bash:test-4512 splitStatements:true endDelimiter:\nGO
UPDATE User
SET FirstName='${MyProp}'

scripts/feat2/change2-1.sql:
--liquibase formatted sql

--changeset bash:test-4512 splitStatements:true endDelimiter:\nGO
UPDATE User
SET FirstName='${MyProp}'

Can you please help.
Thanks
Bash

Hi @bashiransari Thanks for taking the time to submit this.  I'll take a closer look once I am able to setup and recreate this issue.

Hi @bashiransari . Two more questions as I try to address and see what can be done.  What version of liquibase were you using?  And what database were you trying this against?

@bashiransari Thank you again for posting your issue. I am going to close this as it has been inactive for a while. Please don't hesitate to open a new issue if you continue to face the issue. And I also encourage you to check out the Liquibase Forum -- it is becoming a solid resource for asking/answering questions.


[Feature Request]: Display current file with file type

Contact Details
No response
Is your feature request related to a problem?
Difficult for user to easily understand the file they are currently working on.
Describe the solution you would like!
Display in navbar? On questionmark icon?
Additional context!
No response
Host
Applies to All
Host Details
.

Done, will be part of the next release


Update message.js

Added a bit of code (prefix.toLowerCase()).
That line of code allows the user to write the prefix in every case (e.g. d! and D!). This is useful if you are on mobile and you do have an autocorrect in keyboard.
Please describe the changes this PR makes and why it should be merged, as well as any and all proof of successful tests:
As mentioned above, this makes the prefix possible to write in every case (the prefix is case insensitive).
Semantic versioning classification:

[x] This PR changes the framework's interface (methods or parameters added)

[ ] This PR includes breaking changes (methods removed or renamed, parameters moved or removed)

[ ] This PR only includes non-code changes, like changes to README, etc.

I'm not sure why you're adding .toLowerCase() like that, the code is perfectly fine and functional as it is, I won't close this PR yet but please explain the motivation behind PR'ing this change.

Not on my watch.


A few questions about VexiiRiscv L1 caches and Tilelink

Trying to migrate my hobby project SoC from VexRiscv to VexiiRiscv. I suspect there is a bug in FetchL1Plugic:
After fetching first few commands FetchL1Plugin produces unknown ('xxxx) output if cache memory was not zero-initialized.
Simulation in iverilog:

After a few clock cycles 'xxxx propagates to registers in PcPlugin and simulation gets stuck.
But if I either set bootMemClear = true or disable cache (fetchL1Enable = false) in ParamSimple, it works fine.

Hi,
bootMemClear is the intended way to avoid those x-prop.
Overall, as far i looked into the x-prop happening in Vexiiriscv (with bootMemClear = false), they all look like false bug only induced by x-prop creating impossible cases.
In other words, x-prop creating simulation only bugs.
All the test i run VexiiRiscv on, are run by Verilator, which instead of x-prop, use 1 and 0 and randomize all the values at init.
I kinda don't feel great about putting bootMemClear by default, because it consume hardware ressources and timings. Maybe instead i should put a big warning message at the very end of the VexiiRiscv hardware generation to warn about it ?

Trying to migrate my hobby project SoC from VexRiscv to VexiiRiscv

Nice ^^
What SoC / memory bus are you working with ?

In other words, x-prop creating simulation only bugs.
All the test i run VexiiRiscv on, are run by Verilator, which instead of x-prop, use 1 and 0 and randomize all the values at init.

Thanks! Makes perfect sense then.

Maybe instead i should put a big warning message at the very end of the VexiiRiscv hardware generation to warn about it?

Can be enough to mention it in documentation, somewhere near "Run a simulation" section. It would save me some time.

What SoC / memory bus are you working with?

Previously used Axi4, now trying Tilelink.
SpinalHDL components for Tilelink look very nice, but it is not easy to follow all the magic that happens underneath. For example struggling to get the meaning of
// from vexiiriscv/soc/litex/Soc.scala
vexii.lsuL1Bus.setDownConnection(a = withCoherency.mux(StreamPipe.HALF, StreamPipe.FULL), b = StreamPipe.HALF_KEEP, c = StreamPipe.FULL, d = StreamPipe.M2S_KEEP, e = StreamPipe.HALF)
vexii.dBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S_KEEP)

and understand why it should be written exactly this way.
By the way, what is the best place to ask questions? Here? Or maybe in SpinalHDL google group?

I have a few probably stupid questions.

setDownConnection is a way to ask the interconnect to add some pipelining stages between lsuL1Bus and the address decoder which will serve the down connections.

Do I understand right that lsuL1Bus is the bus from cache to memory, and when cache is enabled dBus is used only for non-cachable regions?
I.e.
     ->  fetch L1 cache -> iBus -> memory
cpu  ->  LSU L1 cache -> lsuL1Bus -> memory
     ->              dBus       -> IO regions

StreamPipe.HALF is a lightweight pipeline stage which fully cut all combinatorial paths.
StreamPipe.FULL is a "heavy weight" one which also cut all combinatorial path
StreamPipe.M2S_KEEP is a ligtweight one which cut the valid + data path, but not the ready path

In https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/stream.html it is written that after halfPipe() the bandwidth divided by two. Half pipe on channel A then should mean that during all write operations it can send each beat of data only on every second clock cycle, and the bus works twice slower than it could. Seems I am missing something... Do maybe all writes go through channel C rather than A?
Also I can not figure out what param.lsuL1Coherency actually change. Let's take several use cases:

Tilelink bus with 2 masters (a. VexiiRiscv core with cache; b. video controller) and one slave (memory). Video controller makes only READ requests, but should trigger writeback if the requested data is cached and modified by the core.
Same as before, but add DMA controller to the same bus. It does both READ and WRITE operations (should trigger writeback & invalidate in VexiiRiscv cache), but DMA controller doesn't have its own cache.
Add to the same bus a second VexiiRiscv core that also has a cache.

Do all the use cases require lsuL1Coherency to be enabled? Or only the last one?
My current use case is the first one. I have video controller with Axi4ReadOnly interface and I am trying to figure out how to connect it to tilelink and make sure that cpu will writeback cached data when needed.

By the way, what is the best place to ask questions? Here? Or maybe in SpinalHDL google group?

Github issue are good, this repo is good aswell ^^

I renamed the issue to better match the content :-)

Hi,

Do I understand right that lsuL1Bus is the bus from cache to memory, and when cache is enabled dBus is used only for non-cachable regions?

Yes

Do maybe all writes go through channel C rather than A?

Yes right for coherent caches. They send "aquire" requests on channel A (single beat), receive "aquire" responses on channel D (multi beat), and "release" dirty/clean cache lines on channel C.

Tilelink bus with 2 masters (a. VexiiRiscv core with cache; b. video controller) and one slave (memory). Video controller makes only READ requests, but should trigger writeback if the requested data is cached and modified by the core.

Right

Same as before, but add DMA controller to the same bus. It does both READ and WRITE operations (should trigger writeback & invalidate in VexiiRiscv cache), but DMA controller doesn't have its own cache.

Right

Do all the use cases require lsuL1Coherency to be enabled? Or only the last one?

All cases. As soon as you have multiple masters (cpu, dma), and a given CPU has a data cache, then that CPU need lsuL1Coherency. (or it will need to do cache flush/invalidate in software)

My current use case is the first one. I have video controller with Axi4ReadOnly interface and I am trying to figure out how to connect it to tilelink and make sure that cpu will writeback cached data when needed.

One reference for that is the litex SoC.scala.
What matter is that the CPU / DMA busses are merged together and then go into either a CacheFiber (l2), either into the HubFiber (no l2).
Those CacheFiber / HubFiber will handle all the coherency channel (a,b,c,d,e) and provide to the memory system (DDR) only the regular channel to do get/put (a,d).

Thanks for the answers!

(or it will need to do cache flush/invalidate in software)

By the way, does VexiiRiscv support any cache flush instructions? I've seen only fence.i and sfence.vma, but they are not about flushing particular cache lines.
And how fetch L1 interacts with lsu L1 if lsuL1Coherency is disabled? Does fence.i flushes the whole lsu L1 to ensure that iBus will see correct data?

What matter is that the CPU / DMA busses are merged together and then go into either a CacheFiber (l2), either into the HubFiber (no l2).

Ah! That's what I missed!
If DMA uses only A,D channels and only simple get/put requests, will CacheFiber/HubFiber automatically generate flush/invalidate requests to CPU?

By the way, does VexiiRiscv support any cache flush instructions? I've seen only fence.i and sfence.vma, but they are not about flushing particular cache lines.

Currently, there is nothing to flush particular cache lines. Idealy, CMO would need to be implemented to allow VexiiRiscv usages without memory coherency.
Todo ^^

Does fence.i flushes the whole lsu L1 to ensure that iBus will see correct data?

Yes

If DMA uses only A,D channels and only simple get/put requests, will CacheFiber/HubFiber automatically generate flush/invalidate requests to CPU?

Yes

The HubFiber will generate flush / invalidate for every request, while the CacheFiber has a dictionnary which track which cache has what, and so, will only generate usefull flush / invalidate requests

Idealy, CMO would need to be implemented to allow VexiiRiscv usages without memory coherency.
Todo ^^

CMO would be great! I hope it will also allow to avoid useless read-before-write requests to memory - for example when memcpy is going to fill the whole cache line with new data, but cpu decides to read this cache line from memory first.

The HubFiber will generate flush / invalidate for every request, while the CacheFiber has a dictionnary which track which cache has what, and so, will only generate usefull flush / invalidate requests

Interesting. Does it mean that if I use HubFiber it can make sense to connect iBus around it to reduce the number of invalidate requests?
                DMA  ------------------> TilelinkHub -\
    / ->  lsu L1 cache   -> lsuL1Bus -/                >--- memory
CPU | ->  fetch L1 cache -> iBus ---------------------/
    \ --------------------> dBus ----> IO

Or fence.i flushes the whole lsu L1 only if coherency is off?

I hope it will also allow to avoid useless read-before-write requests to memory - for example when memcpy is going to fill the whole cache line with new data, but cpu decides to read this cache line from memory first.

Ahhh that is because now, the cache is implemented as "write-back"
So, cache line will always be readed, even if the CPU only write in it. It won't go away
Write-through cache don't have that issue, but instead, they spam the memory system with little write requests.

Interesting. Does it mean that if I use HubFiber it can make sense to connect iBus around it to reduce the number of invalidate requests?

Hmmm, if you have multiple CPU, you would then need to other CPU to manuly flush themself if they modify code sections.
But else, yes.
fence.i always flush the whole D$ + I$ for both cases.
Fondamentaly, when coherency is on, it wouldn't be necessary to flush D$

So, cache line will always be readed, even if the CPU only write in it. It won't go away

I mean that there can be a special instruction that makes L1 cache think that the cache line is already loaded without an a actual read. I've looked through CMO spec and see that it doesn't have it. But can be a custom instruction.
char *src = ..., *dst = ...;
for (int i = 0; i < size / 64; ++i) {
  fakeReadCacheLine(dst);  // custom instruction
  for (int j = 0; j < 64; j += 4) *(int*)(dst + j) = *(int*)(src + j);
  src += 64, dst += 64;
}

Ahhhhh lol, i didn't know about it.
Yes there could be a custom instruction for that.

I am stuck with it. Could you please help to figure out why it doesn't work?
I want to connect a blackbox to a tilelink bus. It will use only 256-byte read requests.
class VideoController extends BlackBox {
  val io = new Bundle {
    ...
    val tl_bus = master(tilelink.Bus(tilelink.BusParameter(
      addressWidth = 32,
      dataWidth    = 64,
      sizeBytes    = 256,
      sourceWidth  = 0,
      sinkWidth    = 0,
      withBCE      = false,
      withDataA    = false,
      withDataB    = false,
      withDataC    = false,
      withDataD    = true,
      node         = null
    )))
  }
  noIoPrefix()
  mapClockDomain(clock=io.clk, reset=io.reset)
}

  val coherent_bus = tilelink.fabric.Node().forceDataWidth(64)
  val mem_bus = tilelink.fabric.Node().forceDataWidth(64)

  val tilelink_hub = new tilelink.coherent.HubFiber()
  tilelink_hub.up << coherent_bus
  mem_bus << tilelink_hub.down

  val video_ctrl = new VideoController()
  val video_bus = tilelink.fabric.Node.down()
  val video_bus_fiber = fiber.Fiber build new Area {
    video_bus.m2s forceParameters tilelink.M2sParameters(
      addressWidth = 32,
      dataWidth = 64,
      masters = List(
        tilelink.M2sAgent(
          name = video_ctrl,
          mapping = List(
            tilelink.M2sSource(
              id = SizeMapping(0, 1),
              emits = tilelink.M2sTransfers(get = tilelink.SizeRange(256, 256))
            )
          )
        )
      )
    )
    video_bus.s2m.supported load tilelink.S2mSupport.none()
    video_bus.bus << video_ctrl.io.tl_bus
  }
  coherent_bus << video_bus  // this line causes error

The error (the first one, there are many of them) is
[error]  Error detected in phase PhaseCreateComponent
[error] ********************************************************************************
[error] ********************************************************************************
[error]
[error] Bundle assignment is not complete. toplevel/video_bus_noDecoder_toDown_d_payload : ChannelD need 'data' but toplevel/video_bus_to_coherent_bus_up_bus_d_payload : ChannelD doesn't provide it.
[error]     spinal.lib.Stream.connectFrom(Stream.scala:317)
[error]     spinal.lib.Stream.$less$less(Stream.scala:117)
[error]     spinal.lib.Stream.$greater$greater(Stream.scala:122)
[error]     spinal.lib.bus.tilelink.Bus.$less$less(Bus.scala:418)
[error]     spinal.lib.bus.tilelink.fabric.Node$$anon$2$$anon$6.<init>(Node.scala:213)
[error]     spinal.lib.bus.tilelink.fabric.Node$$anon$2.$anonfun$noDecoder$1(Node.scala:207)
[error]     spinal.lib.bus.tilelink.fabric.Node$$anon$2.<init>(Node.scala:207)
[error]     spinal.lib.bus.tilelink.fabric.Node.$anonfun$thread$1(Node.scala:77)

Ahhhh i think the reason is that the memory coherency hub / l2  can't handle memory requests bigger than one cache line. So no memory request more than 64 bytes is allowed.
So either :

you need to tilelink.SizeRange(64)
Would need to design a bridge to split memory 256 bytes memory accesses into 64 bytes ones, but overall, i think the best is realy to stick to "no more than 64 bytes". That allows to stream line a lot of things

Yes, changed to 64 and now it successfully generates verilog! Thanks!
By the way, is it possible to generate a more explanatory error message in such situation? No idea how would I debug it without your help.

I will take a look tomorrow ^^
The situation right now is that  Hub filter memory accesses to only allow the compatible one, which create a video DMA with no memory access at all, => no read / no write => withDataD = false

Would need to design a bridge to split memory 256 bytes memory accesses into 64 bytes ones, but overall, i think the best is realy to stick to "no more than 64 bytes". That allows to stream line a lot of things

The only reason to use big requests was that in this case memory throughput is a bit higher. But it is not that significant.

One thing, i recently updated the documentation, in particular around the MicroSoc, you may find interresting things there, in particular :
https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/Soc/microsoc.html#adding-a-custom-peripheral
I recently added a tilelink video DMA, see :
https://github.com/SpinalHDL/VexiiRiscv/blob/dev/src/main/scala/vexiiriscv/soc/litex/Soc.scala#L152
Good luck :D

Thanks!
I used both MicroSoc and litex SoC as an examples.
Things like demo.node at 0x10003000 of bus32 look as magic. It is really nice and convenient. But when I do something wrong and the magic breaks, it is sometimes hard to dig into details. So for now my preferred approach is to write custom modules in verilog and connect them together using SpinalHDL.

But when I do something wrong and the magic breaks, it is sometimes hard to dig into details

Yes i agree. Error reporting isn't great when it goes into Fiber / Tilelink stuff.
For the Raw SpinalHDL things using component and so on, it should be good :D

fence.i always flush the whole D$ + I$ for both cases.

Actually fence.i doesn't flush D$. At least if coherency is enabled. Checked experimentally. So I have to connect iBus to the tilelink hub rather than to memory directly.

Ahhh right, i just checked the code again, when coherency is enabled, the LsuPlugin will instead just wait that the storebuffer are drained out.
    val coherentFlusher = l1.coherency.get generate new Area{
      invalidationPorts.foreach(_.cmd.ready := withStoreBuffer.mux(storeBuffer.empty, True))
    }

Hi! Sometimes a have deadlocks somewhere in my SoC. I suppose they are caused by attempts to read or write invalid memory regions that are not connected to any slave interfaces. The problem is that I don't have a way to debug it: in my setup there is no integration with standard tools and no easy way for things like logic analyzer over jtag. And scenarios are too complicated for simulation (e.g. boot linux and run gcc on device).
Is there a way to add to tilelink hub a default slave interface that will be used if the address is not mapped to anything else? I want to add a module that catches all invalid requests and sends debug information via UART.

It seems that this time I faced an actual bug in VexiiRiscv.
param.lanes = 2 causes deadlock in some cases.
Unfortunately I can't provide a simple reproducing example. The deadlock happens when I run gcc on device (compiling a trivial hello world). Can't simulate in iverilog - it would take days of single-thread simulation. However with param.lanes = 1 everything works fine, and with param.lanes = 2 when I run gcc there is always a deadlock (though linux boots and some other programs I tried work fine).
VexiiParams: https://github.com/petrmikheev/endeavour/blob/master/rtl/spinal/src/main/scala/endeavour/VexiiCore.scala#L40
The script I use to compile rv32 gcc: https://github.com/petrmikheev/endeavour/blob/master/scripts/build_toolchain.sh

Ahhh,
I will try dual issue on hardware, running debian to see how well it goes, and if it crash. That should be a good test case :)
Hopefully i can reproduce.
How does it crash freeze, i mean, can you reproduce easily ? is it kinda always dead lock on the same app ?

Another question is : Are all the timings passing place / route with positive slack ?

How does it crash freeze, i mean, can you reproduce easily ? is it kinda always dead lock on the same app ?

Yes, always dead lock on the same place on every attempt. And it is definitely not just an infinite loop in software - it stopped reacting to timer interrupts.

Another question is : Are all the timings passing place / route with positive slack ?

Timing analyzer reports that it should work fine even at 85C temperature.

In particular, which app is freezing ?

Can you send me your linux / buildroot binaries ?
Sometime, bugs only appear is specific binaries versions

In particular, which app is freezing ?

Console gcc!
In particular - the binary /usr/libexec/gcc/riscv32-unknown-linux-gnu/13.2.0/cc1.
I build it using https://github.com/riscv/riscv-gnu-toolchain (commit 6d7b5b7).

Can you send me your linux / buildroot binaries ?

I don't use buildroot... And an attempt to reproduce my setup in all details would require soldering.
The goal of my project was to go the whole path on my own: design fpga board, solder it, design SoC capable to run linux, write linux drivers for my custom peripherals, implement sbi and bootloader, manually bring together linux kernel and all the software (to better understand how linux works), and finally to be able to write and compile code directly on the device.
And (if param.lanes = 1) it works!

But reproducing the bug on your side can be a big problem. My only hope is that if you use same VexiiRiscv params, run 32-bit debian, and try to compile hello world with gcc, the freeze will happen too.

I tried some configs running 64 bits debian :
--mmu-sync-read  --with-mul --with-div --allow-bypass-from=0 --performance-counters=0 --fetch-l1 --fetch-l1-ways=2 --lsu-l1 --lsu-l1-ways=2  --with-lsu-bypass --relaxed-branch --with-rva --with-supervisor --fetch-l1-ways=4 --fetch-l1-mem-data-width-min=64 --lsu-l1-ways=4 --lsu-l1-mem-data-width-min=64 --xlen=64 --with-rvc --with-rvf --with-rvd --fma-reduced-accuracy --fpu-ignore-subnormal --with-btb --with-ras --with-gshare --fetch-l1-hardware-prefetch=nl --fetch-l1-refill-count=3 --fetch-l1-mem-data-width-min=128 --lsu-l1-mem-data-width-min=128 --lsu-software-prefetch --lsu-hardware-prefetch rpt --performance-counters 9 --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 4 --lsu-l1-writeback-count 4 --lsu-l1-store-buffer-slots=4 --lanes=2 --decoders=2 --with-late-alu --relaxed-div

So, mainly, dual issue, with late-alu, and a few other things.
So far all seems to work well. But i forgot to try with the --with-dispatcher-buffer
Synthesis in progress XD

One thing i can see on your side, is that you only have 1 way of 4Kb for each i$ d$
This may lead to some dead lock when you have the store buffer enabled (seems it isn't your case)
But still, can you try with 4 ways for both i$d$ ?

Also, which version of linux do you use ?

I tried some configs running 64 bits debian : ...

In your options string there are some duplicates:
--fetch-l1-ways=2  ... --fetch-l1-ways=4
--lsu-l1-ways=2 ... --lsu-l1-ways=4
--fetch-l1-mem-data-width-min=64 ... --fetch-l1-mem-data-width-min=128
--lsu-l1-mem-data-width-min=64 ... --lsu-l1-mem-data-width-min=128
--performance-counters=0 ... --performance-counters 9

I guess only the last value of each setting is used?

Also, which version of linux do you use ?

Linux kernel 6.9.2

This may lead to some dead lock when you have the store buffer enabled (seems it isn't your case)
But still, can you try with 4 ways for both i$d$ ?

Tried now, unfortunately freezes anyway.
By the way, what is store buffer and when it is recommended to use it? I haven't found anything related in documentation.
Also I have questions about some other settings:
--fetch-l1-refill-count=3
--lsu-l1-refill-count 4 --lsu-l1-writeback-count 4

Is it the number of refill/writeback transaction that can be in-flight simultaneously?
Why you set fetch-l1-refill-count to 3? Seems I$ can request maximum 2 cache lines at the same time - the current one, and the next one if prefetcher is enabled.
--lsu-software-prefetch --lsu-hardware-prefetch rpt

Documentation explains hardware prefetch, but what is software prefetch? Can it be useful to enable both at the same time?

Hi,
So i just tested much on ti375 fpga, running debian rv64imafdc with dual issue + late-alu + linux 6.10.0-rc2+.
Didn't had any bug so far.
Maybe the bug is somewere else than in the CPU, but was not visible with the single issue config, as things where behaving with different timings ?

I guess only the last value of each setting is used?

Yes

By the way, what is store buffer and when it is recommended to use it?

I just pushed some doc about it :
https://github.com/SpinalHDL/VexiiRiscv-RTD/commit/014aa3679a4b1bdf450d060a4cabec78b8453828
https://github.com/SpinalHDL/VexiiRiscv-RTD/commit/c49000edc8e3fe50ffe11bffb81df47eef802001

Is it the number of refill/writeback transaction that can be in-flight simultaneously?

Yes

Why you set fetch-l1-refill-count to 3? Seems I$ can request maximum 2 cache lines at the same time - the current one, and the next one if prefetcher is enabled.

Not always enough:

Imagine :

slot 0 used as the prefetch of the next line before a jump
slot 1 used for the cache line where you jump
slot 2 used for the next cache line after the jump

Documentation explains hardware prefetch, but what is software prefetch? Can it be useful to enable both at the same time?

It allows the user to explicitly prefetch a cache line via a dedicated instruction (RISC-V CMO)
It is usefull for access patterns which do not follow a regular stride (not predictable via RPT)
Typicaly some software which scan a  linked list could use this to prefetch the next element of the linked list.

Maybe the bug is somewere else than in the CPU, but was not visible with the single issue config, as things where behaving with different timings ?

Maybe... Though I have no idea where to look. Seems that outside of the core in the dual-issue case the only visible difference should a more frequent memory requests. But it doesn't look like deadlock somewhere in memory system - when CPU freezes video controller is still able to read framebuffer and I see no artifacts on the screen.
Tried to add  fetchL1RefillCount = 3; lsuL1RefillCount = 4; lsuL1WritebackCount = 4, no difference.

I just pushed some doc about it :

Thanks a lot!

--lsu-l1-store-buffer-ops=X
Specify how many store miss can be pushed in the store buffer (disabled/0 by default)

So --lsu-l1-store-buffer-ops=32 means that up to 32 sw/sh/sb operations can be queued if the destination is not in D$? What happens in read-after-write case (e.g. lw right after sw with the same address)? Will it search the new value in the store buffer? Or just lock while store buffer is not empty? Are there cases when store buffer can lead to slow downs on read operations?

--lsu-software-prefetch
Enable RISC-V CMO for software prefetching in the D$

It allows the user to explicitly prefetch a cache line via a dedicated instruction (RISC-V CMO)

Ah! Nice! Isn't it a partial implementation (without prefetch.i) of Zicbop extension? If I understand correctly it can be enabled in gcc by adding _zic64b_zicbop to -march string (gcc options). Somehow from your previous messages I thought that no cache-related instructions are implemented yet.
Maybe mention in documentation that it is Zicbop? And probably implement prefetch.i (can be no-op) - to prevent crashing if gcc emits it when zicbop is enabled.
And a feature request from me: would be great to have cbo.zero. It is almost the same that I mentioned above and it seems to be easy to add. I think (not sure if compilers can do it right now) that aside of memset it can speedup memcpy up to 30% - by avoiding reading memory at destination location.

Maybe... Though I have no idea where to look. Seems that outside of the core in the dual-issue case the only visible difference should be a more frequent memory requests. But it doesn't look like deadlock somewhere in memory system - when CPU freezes video controller is still able to read framebuffer and I see no artifacts on the screen.

Weird.
Did you tried to inspect the CPU state via openocd + jtag ?
To see if the CPU is deadlocked in a hard way, or if there is a software lockup ?
That could already rule out a lot :)

So --lsu-l1-store-buffer-ops=32 means that up to 32 sw/sh/sb operations can be queued if the destination is not in D$?

Yes

What happens in read-after-write case

Then the load will be cancel, then the CPU will retry and hopefully successed. else retry again and again

Will it search the new value in the store buffer?

No, to expensive in fpga hardware ^^
I guess on ASIC they would do that.

Or just lock while store buffer is not empty?

it will retry again and again (lazy implementation)

Are there cases when store buffer can lead to slow downs on read operations?

Hmmm
Maybe a bit for miss on "store X" followed by "load X", but probably not a big deal.

Ah! Nice! Isn't it a partial implementation (without prefetch.i) of Zicbop

right.

And a feature request from me: would be great to have cbo.zero. It is almost the same that I mentioned https://github.com/SpinalHDL/VexiiRiscv/issues/31#issuecomment-2445149030 and it seems to be easy to add. I think (not sure if compilers can do it right now) that aside of memset it can speedup memcpy up to 30% - by avoiding reading memory at destination location.

Yes right, it would probably help a lot for those operation.
It isn't realy planned so far, have a lot of other pending things XD
But for sure it would be nice to have.

Did you tried to inspect the CPU state via openocd + jtag ?
To see if the CPU is deadlocked in a hard way, or if there is a software lockup ?
That could already rule out a lot :)

I've tried it now. Yes, it is deadlocked in a hard way :(
(gdb) c
Continuing.
^C
Program received signal SIGINT, Interrupt.
0xc026f910 in ?? ()
(gdb) x/10i ($pc-8)                     // just to illustrate that debugger works
   0xc026f908:	fence	i,ir            // it is not the code that freezes
   0xc026f90c:	srli	a4,a5,0xb
=> 0xc026f910:	andi	a4,a4,521
   0xc026f914:	bnez	a4,0xc026f902
   0xc026f916:	addi	s5,s5,1
   0xc026f918:	xor	s3,s3,s2
   0xc026f91c:	bne	s4,s5,0xc026f8c6
   0xc026f920:	mv	s8,s3
   0xc026f922:	lw	a6,-88(s0)
   0xc026f926:	lw	a2,-92(s0)
(gdb) c
Continuing.
^Cunable to halt hart 0                 // here I tried to interrupt after the freeze
  dmcontrol=0x00000001
  dmstatus =0x00430c82
Could not read registers; remote failure reply 'E0E'
(gdb)

Does the EmbeddedRiscvJtag/openocd/gdb chain support anything like "run next N instructions and stop"? Then I would try to find the place it freezes with a binary search. When I try si it works the same as c - just continues evaluation until I manually interrupt it.

hmm going with GDB is a bad idea in this kind of case
Better go with a more lightweight telnet localhost 4444 directly to openocd, and then from there :
halt
reg pc
step
reg pc
things like that. It has much less side effect than GDB

run next N instructions and stop"

Maybe the openocd "step" instruction has a count argument ? i don't know
Could you try with openocd telnet ? To avoid the gdb noise.
In particular, if you can retreive which is faulty PC, can you send me your vmlinux  elf binary ?

Do you handle unaligned load/store emulation in your SBI ?

No, my sbi trap handler just prints error message in case of unaligned access. Here it is not the case. I suspect that there is some specific sequence of instructions that can lead to hardware deadlock in dual-issue VexiiRiscv. Need only to find the exact place it freezes to check it.

Let me know how things goes, i'm realy trying to get VexiiRiscv as bug free as possible.
Also, if we have to probe things in order to progress i may have a few signals which could help

Also, note that having a setup where you can reproduce a bug in a non-random way, is valuable, backup all the binaries / elf files :D

Let's try to reproduce it on your side.
Here is 40MB initrd image that contains ext2 filesystem with rv32 cc1 binary and a few libraries it needs: cc1.initrd.
Linux kernel is not included because I use a custom uart controller with custom uart driver which will not work with any other hardware.
I hope this will be enough to reproduce the freeze:

VexiiRiscv rv32imacsu with param.lanes = 2
At least 128MB RAM
More or less any rv32 linux kernel with ext2 support and BLK_DEV_RAM=y BLK_DEV_RAM_SIZE >= 40MB
Copy initrd to RAM and start the kernel with "root=/dev/ram" in bootargs and proper initrd-start/initrd-end values.

My DTS (all peripherals except UART are disabled)
// SPDX-License-Identifier: GPL-3.0
/dts-v1/;

/ {
  #address-cells = <1>;
  #size-cells = <1>;
  model = "Endeavour";

  chosen {
    bootargs = "console=ttyS0,sbi:115200e earlycon=endeavour_sbi debug root=/dev/ram";
    linux,initrd-start = <0x85000000>;
    linux,initrd-end   = <0x87800000>;
  };

  cpus {
    #address-cells = <1>;
    #size-cells = <0>;
    timebase-frequency = <1000000>;
    cpu0: cpu@0 {
      device_type = "cpu";
      reg = <0>;
      status = "okay";
      compatible = "riscv";
      riscv,isa-base = "rv32i";
      riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei";
      mmu-type = "riscv,sv32";
      intc0: interrupt-controller {
        #interrupt-cells = <1>;
        interrupt-controller;
        compatible = "riscv,cpu-intc";
      };
    };
  };

  plic: interrupt-controller@4000000 {
    compatible = "riscv,plic0";
    reg = <0x4000000 0x4000000>;
    #address-cells = <0>;
    #size-cells = <0>;
    #interrupt-cells = <1>;
    interrupt-controller;
    interrupts-extended = <&intc0 9>;
    riscv,ndev = <4>;
  };

  uart: serial@1000 {
    compatible = "endeavour,uart";
    reg = <0x1000 12>;
    interrupts-extended = <&plic 1>;
  };

  memory@80000000 {
    device_type = "memory";
    reg = <0x80000000 0x08000000>;
  };

  reserved-memory {
    #address-cells = <1>;
    #size-cells = <1>;
    ranges;
    framebuffer@80000000 {
      no-map;
      reg = <0x80000000 0x400000>;
    };
  };

};

/sbin/init in this image is sh script:
#!/bin/sh

mount -t sysfs none /sys
mount proc /proc -t proc
mount -o remount,noatime,rw /   # remount initrd as rw, otherwise cc1 can't create output file
/cc1 -v -o test.s test.c       # freeze happens here
echo OK

In my case the output is the following:
...
[    2.790347] RAMDISK: ext2 filesystem found at block 0
[    2.790775] RAMDISK: Loading 40960KiB [1 disk] into ram disk...
[    4.874120]
[    7.597555]
[   10.310734]
[   13.510638]
[   16.388365] done.
[   17.285606] VFS: Mounted root (ext2 filesystem) readonly on device 1:0.
[   17.286655] devtmpfs: error mounting -2
[   17.288953] Freeing unused kernel image (initmem) memory: 132K
[   17.289409] Kernel memory protection not selected by kernel config.
[   17.289889] Run /sbin/init as init process
[   17.290206]   with arguments:
[   17.290455]     /sbin/init
[   17.290705]   with environment:
[   17.290955]     HOME=/
[   17.291184]     TERM=linux
ignoring nonexistent directory "/home/petya/rv32imac-linux-toolchain/native/lib/gcc/riscv32-unknown-linux-gnu/13.2.0/include"
ignoring nonexistent directory "/usr/local/include"
ignoring nonexistent directory "/home/petya/rv32imac-linux-toolchain/native/include"
ignoring nonexistent directory "/home/petya/rv32imac-linux-toolchain/native/lib/gcc/riscv32-unknown-linux-gnu/13.2.0/include-fixed"
ignoring nonexistent directory "/home/petya/rv32imac-linux-toolchain/native/riscv32-unknown-linux-gnu/include"
ignoring nonexistent directory "/home/petya/rv32imac-linux-toolchain/native/include"
#include "..." search starts here:
#include <...> search starts here:
End of search list.
cc1: error: no include path in which to search for stdc-predef.h
 main
Analyzing compilation unit      <= after this line it freezes and doesn't print OK

I hope it will not be just a waste of your time. I checked all that I could and everything looks like a deadlock in VexiiRiscv, but given the stupidity of some of my bugs I will not be very surprised if something is wrong on my side.

Linux kernel is not included because I use a custom uart controller with custom uart driver which will not work with any other hardware.

Hmm, but i could use the SBI putc/getc instead, isn't it (hvc0)?
As long as it is enabled in the linux kernel.

Hmm, but i could use the SBI putc/getc instead, isn't it (hvc0)?
As long as it is enabled in the linux kernel.

I had it disabled, but now has enabled and rebuilt the kernel. Image.gz

[Progress] Verilator compilation started
[info] Found cached verilator binaries
[Progress] Verilator compilation done in 350.358 ms
[Progress] Start MinimalLinuxSim test simulation with seed 42
Loading sbi.bin DONE
Loading /home/petya/endeavour-tools/linux_kernel/arch/riscv/boot/Image DONE
Loading /home/petya/endeavour-tools/cc1.initrd DONE
Start
[SBI] Probing extension 0x735049
[SBI] Probing extension 0x52464E43
[    0.000000] Linux version 6.9.2 (petya@petya-ThinkPad-P52) (riscv32-unknown-linux-gnu-gcc (gc891d8dc23e) 13.2.0, GNU ld (GNU Binutils) 2.42) #27 Thu Dec  5 17:51:31 CET 2024
[    0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80400000
[    0.000000] Machine model: Endeavour
[    0.000000] SBI specification v0.2 detected
[    0.000000] SBI implementation ID=0x0 Version=0x0
[    0.000000] SBI TIME extension detected

... 10 hours later ...

[   16.499706] Run /sbin/init as init process
[   16.499997]   with arguments:
[   16.500222]     /sbin/init
[   16.500449]   with environment:
[   16.500680]     HOME=/
[   16.500893]     TERM=linux
ignoring nonexistent directory "/home/petya/rv32imac-linux-toolchain/native/lib/gcc/riscv32-unknown-linux-gnu/13.2.0/include"
ignoring nonexistent directory "/usr/local/include"
ignoring nonexistent directory "/home/petya/rv32imac-linux-toolchain/native/include"
ignoring nonexistent directory "/home/petya/rv32imac-linux-toolchain/native/lib/gcc/riscv32-unknown-linux-gnu/13.2.0/include-fixed"
ignoring nonexistent directory "/home/petya/rv32imac-linux-toolchain/native/riscv32-unknown-linux-gnu/include"
ignoring nonexistent directory "/home/petya/rv32imac-linux-toolchain/native/include"
#include "..." search starts here:
#include <...> search starts here:
End of search list.
[01m[Kcc1:[m[K [01;31m[Kerror: [m[Kno include path in which to search for stdc-predef.h
 main
Analyzing compilation unit
[Error] Simulation failed at time=18854063680
[error] spinal.sim.SimFailure: Vexii hasn't commited anything for too long, waiting on uop 0xBC69
[error] 	at spinal.core.sim.package$.simFailure(package.scala:214)
[error] 	at vexiiriscv.test.VexiiRiscvProbe.$anonfun$checkCommits$2(VexiiRiscvProbe.scala:553)
[error] 	at vexiiriscv.test.VexiiRiscvProbe.$anonfun$checkCommits$2$adapted(VexiiRiscvProbe.scala:547)
[error] 	at scala.collection.TraversableLike$WithFilter.$anonfun$foreach$1(TraversableLike.scala:985)
[error] 	at scala.collection.IndexedSeqOptimized.foreach(IndexedSeqOptimized.scala:36)
[error] 	at scala.collection.IndexedSeqOptimized.foreach$(IndexedSeqOptimized.scala:33)
[error] 	at scala.collection.mutable.ArrayOps$ofRef.foreach(ArrayOps.scala:198)
[error] 	at scala.collection.TraversableLike$WithFilter.foreach(TraversableLike.scala:984)
[error] 	at vexiiriscv.test.VexiiRiscvProbe.checkCommits(VexiiRiscvProbe.scala:547)
[error] 	at vexiiriscv.test.VexiiRiscvProbe.$anonfun$new$2(VexiiRiscvProbe.scala:630)
[error] 	at spinal.core.sim.package$SimClockDomainPimper.$anonfun$onSamplings$2(package.scala:1111)
[error] 	at spinal.core.sim.package$SimClockDomainPimper.$anonfun$onSamplings$2$adapted(package.scala:1111)
[error] 	at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
[error] 	at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
[error] 	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
[error] 	at spinal.core.sim.package$SimClockDomainPimper.$anonfun$onSamplings$1(package.scala:1111)
[error] 	at spinal.core.sim.package$$anon$1.update(package.scala:248)
[error] 	at spinal.sim.SimManager.runWhile(SimManager.scala:340)
[error] 	at spinal.sim.SimManager.runAll(SimManager.scala:262)
[error] 	at spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:614)
[error] 	at spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:587)
[error] 	at b3.MinimalLinuxSim$.delayedEndpoint$b3$MinimalLinuxSim$1(MinimalLinuxSim.scala:92)
[error] 	at b3.MinimalLinuxSim$delayedInit$body.apply(MinimalLinuxSim.scala:89)
[error] 	at scala.Function0.apply$mcV$sp(Function0.scala:39)
[error] 	at scala.Function0.apply$mcV$sp$(Function0.scala:39)
[error] 	at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:17)
[error] 	at scala.App.$anonfun$main$1$adapted(App.scala:80)
[error] 	at scala.collection.immutable.List.foreach(List.scala:431)
[error] 	at scala.App.main(App.scala:80)
[error] 	at scala.App.main$(App.scala:78)
[error] 	at b3.MinimalLinuxSim$.main(MinimalLinuxSim.scala:89)
[error] 	at b3.MinimalLinuxSim.main(MinimalLinuxSim.scala)
[error] 	at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
[error] 	at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
[error] 	at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
[error] 	at java.base/java.lang.reflect.Method.invoke(Method.java:569)
[error] stack trace is suppressed; run last Compile / runMain for the full output
[error] (Compile / runMain) spinal.sim.SimFailure: Vexii hasn't commited anything for too long, waiting on uop 0xBC69
[error] Total time: 34371 s (09:32:51), completed Dec 25, 2024, 2:03:03 PM

Full code of MinimalLinuxSim (only SpinalHDL and VexiiRiscv, not custom components)
package b3

import java.io.FileInputStream

import spinal.core._
import spinal.core.sim._
import spinal.lib._
import spinal.lib.bus.amba3.apb._
import spinal.lib.bus.tilelink
import spinal.lib.bus.tilelink.fabric.Node
import spinal.lib.bus.misc.SizeMapping

import vexiiriscv.ParamSimple
import vexiiriscv.soc.TilelinkVexiiRiscvFiber
import vexiiriscv.test.VexiiRiscvProbe

class VexiiCore(resetVector: Long) {
  val param = new ParamSimple()
  param.resetVector = resetVector
  param.xlen = 32
  param.hartCount = 1
  param.withCaches
  param.lsuL1Coherency = true

  param.fetchMemDataWidthMin = 64
  param.lsuMemDataWidthMin = 64

  param.withRvc = true
  param.withAlignerBuffer = true
  param.withDispatcherBuffer = true

  param.withMul = true
  param.withDiv = true
  param.withRva = true
  param.withRvZb = false

  param.withMmu = true
  param.withMmuSyncRead

  param.privParam.withSupervisor = true
  param.privParam.withUser = true
  param.privParam.withRdTime = true

  // Performance optimization
  param.decoders = 2
  param.lanes = 2

  param.fetchL1Ways = 4
  param.lsuL1Ways = 4

  param.fetchL1RefillCount = 3
  param.lsuL1RefillCount = 4
  param.lsuL1WritebackCount = 4

  param.withBtb = true
  param.withGShare = true
  param.withRas = true

  param.fetchL1Prefetch = "nl"
  //param.lsuSoftwarePrefetch = true
  param.lsuHardwarePrefetch = "rpt"
  param.lsuStoreBufferSlots = 4
  param.lsuStoreBufferOps = 32

  // fMax optimization
  param.relaxedBranch = true
  param.relaxedShift = true
  param.relaxedSrc = true
  param.relaxedBtb = true
  param.relaxedDiv = true
  param.relaxedMulInputs = true

  param.withLateAlu = true
  param.allowBypassFrom = 0
  param.storeRs2Late = true

  val utime = UInt(64 bits)

  val interrupts = new Bundle {
    val timer = Bool()
    val software = Bool()
    val external = Bool()
  }

  val plugins = param.plugins()
  val core = new TilelinkVexiiRiscvFiber(plugins)
  core.priv match {
    case Some(priv) => new Area {
      val mti, msi, mei, sei = misc.InterruptNode.master()
      mti.flag := interrupts.timer
      msi.flag := interrupts.software
      mei.flag := interrupts.external
      sei.flag := interrupts.external
      priv.mti << mti
      priv.msi << msi
      priv.mei << mei
      priv.sei << sei
      priv.rdtime := utime
    }
    case None =>
  }

  core.iBus.setDownConnection { (down, up) =>
    down.a << up.a.halfPipe().halfPipe()
    up.d << down.d.m2sPipe()
  }
  core.lsuL1Bus.setDownConnection(a = StreamPipe.HALF, b = StreamPipe.HALF_KEEP, c = StreamPipe.FULL, d = StreamPipe.M2S_KEEP, e = StreamPipe.HALF)
  core.dBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S_KEEP)
}

class MinimalLinuxSim extends Component {
  val ramBaseAddr = 0x80000000L
  val ramSize = 128L * 1024L * 1024L

  val utime = Reg(UInt(64 bits)) init(0)
  utime := utime + 1

  val fake_uart_cfg = Reg(Bits(32 bits))
  val timecmp = Reg(UInt(64 bits)) init(0xffffffffl)

  val bus = tilelink.fabric.Node().forceDataWidth(64)
  val cbus = tilelink.fabric.Node()

  val tilelink_hub = new tilelink.coherent.HubFiber()
  tilelink_hub.up << cbus
  bus << tilelink_hub.down

  val cpu = new VexiiCore(resetVector=ramBaseAddr)
  cbus << cpu.core.lsuL1Bus
  cbus << cpu.core.iBus

  cpu.utime := utime
  cpu.interrupts.timer := utime >= timecmp
  cpu.interrupts.software := False
  cpu.interrupts.external := False

  val toApb = new tilelink.fabric.Apb3BridgeFiber()
  toApb.down.addTag(new system.tag.MemoryEndpointTag(SizeMapping(0, 0x4000)))
  toApb.up at (0, 0x4000) of cpu.core.dBus
  val apbFiber = fiber.Handle { new Area {
    val apb = toApb.down.get
    val apbCtrl = Apb3SlaveFactory(apb)
    apbCtrl.read(B(0x80000000l, 32 bits), address = 0x1000) // uart_rx
    apbCtrl.read(B(0, 32 bits), address = 0x1004) // uart_tx
    apbCtrl.driveAndRead(fake_uart_cfg, address = 0x1008)
    apbCtrl.driveAndRead(timecmp(31 downto 0), address = 0x2000)
    apbCtrl.driveAndRead(timecmp(63 downto 32), address = 0x2004)
    val uart_tx_fire = apb.PSEL(0) && apb.PENABLE && apb.PREADY && apb.PWRITE && apb.PADDR === 0x1004
    val uart_tx_value = apb.PWDATA(7 downto 0)
    uart_tx_fire.simPublic
    uart_tx_value.simPublic
  }}

  val ram = new tilelink.fabric.RamFiber(ramSize)
  ram.up at (ramBaseAddr, ramSize) of bus
  fiber.Handle { ram.thread.logic.mem.simPublic() }

  def loadToMem(addr: Long, path: String) = {
    print("Loading %s ".format(path))
    val stream = new FileInputStream(path)
    val size = stream.available()
    val data = new Array[Byte](size)
    stream.read(data)
    stream.close()
    val mem = ram.thread.logic.mem
    val wordSize = mem.width / 8
    for (i <- 0 until (size+wordSize-1) / wordSize) {
      var v: BigInt = 0
      for (j <- 0 until wordSize) { if (i*wordSize+j < size) v = v + (BigInt(data(i*wordSize+j)&0xff) << (j*8)) }
      mem.setBigInt(addr / wordSize + i, v)
    }
    println("DONE")
  }

  def listenUart() = {
    while (true) {
      clockDomain.waitSampling()
      if (apbFiber.uart_tx_fire.toBoolean) {
        val c = apbFiber.uart_tx_value.toInt
        if (c == 10 || (c>=32 && c<=126)) print(c.toChar)
      }
    }
  }
}

object MinimalLinuxSim extends App{
  val sim = SimConfig.withTimeSpec(1 ns, 1 ps).withWave

  sim.compile(new MinimalLinuxSim).doSimUntilVoid("test", seed = 42){dut =>
    val probe = new VexiiRiscvProbe(cpu = dut.cpu.core.logic.core, kb = None)
    probe.autoRegions()

    dut.loadToMem(0, "sbi.bin")
    dut.loadToMem(0x400000l, "/home/petya/endeavour-tools/linux_kernel/arch/riscv/boot/Image")
    dut.loadToMem(0x5000000l, "/home/petya/endeavour-tools/cc1.initrd")

    dut.clockDomain.forkStimulus(20)

    disableSimWave()
    delayed(18853000000L)(enableSimWave())

    dut.listenUart()
  }
}

sbi.bin
Image
cc1.initrd

In 9 hours I'll upload dump of last 1ms of the simulation.

wave.vcd

Nice :D :D :D
GG for the sim setup and capture.
The bug was reproducable in sim via this sequance :
  la x1, data
  nop  // Ensure the memory alignment of the following assembly, to be sure the decoder handle beq and mulh the same cycle
  lw x2, 0(x1) // Generate a late x2 value, this will ensure the beq is scheduled to a late ALU
  beq x2, x2, 1f //That late alu BEQ is taken, which will flush the mulh
  mulh x3, x0, x0 //CPU freeze as the mulh logic which halt the CPU one extra cycle (to help with timeings) was buggy when the instruction is canceled.

A fix is pushed in VexiiRiscv dev
:D THANKS for your perseverance :D

Thanks!


Use a shallow clone for submodules in Netlify

Add --depth 1 to git submodule update --init --recursive, because the revision history of those submodules isn't important.
It's a bit of an optimization.

Thanks @sftim
/lgtm

/approve


Add metadata extractor for caraml-store

[ ] Add unit tests
[ ] Add extractor
[ ] Add README.md in plugins/extractors/caramlstore, defining output
[ ] Register your extractor plugins/extractors/populate.go
[ ] Add extractor the extractor list in docs/reference/extractor.md

feast

caraml-store: https://github.com/caraml-dev/caraml-store
Core gRPC service def<EMAIL_ADDRESS>

CaraML Store does not have any ownership information. @StewartJingga @ravisuhag could you suggest a way to handle this? We won't be able to sync the information into Compass without ownership info.

@sudo-suhas I think we can skip that for now. Compass would provide APIs for people to map owner information.

But it would fail to sync:
Example failure from local run:
INFO[0000] sinking record to compass record="urn:caramlstore:core.s.ng.feast.golabs.io:ml_feature_table:omakase_id_customer_app_interactions"
ERRO[0000] error running sink        error="error sending data: compass returns 400: {\"code\":3,\"message\":\"no user information\",\"details\":[]}" sink=compass

@StewartJingga Is owner information is must in Compass APIs? Is shouldn't be right.

@StewartJingga Is owner information is must in Compass APIs? Is shouldn't be, right?

No, it does not require owner information.
But it does require a header (or in grpc a metadata) to identify who makes the request.
In this case, the required header is X-Shield-User-Id.
Sample recipe
sinks:
      - name: compass
        config:
          host: http://compass.golabs.io
          headers:
            X-Shield-User-Id<EMAIL_ADDRESS>            X-Auth-Email<EMAIL_ADDRESS>          labels:
            entity: "$properties.attributes.entity"
            stream: "$properties.attributes.stream"


Make story to alter padding inside button [Feature]

Is your feature request related to a problem? Please describe.
There needs to be more flexibility in our CTA buttons. The ability to pass smaller and also full width versions would be useful
Describe the solution you'd like
Reduce padding inside button from 18 to 8px. Create version with bespoke padding right / left
Describe alternatives you've considered
none sought
Additional context
Add any other context or screenshots about the feature request here.

Covefed by new feature raised today with specific sizing


Update side-by-side recipe with sign in banner

Summary
Adds EMU sign in banner to side by side banner, to best-effort match the latest designs.
🔗  See it here
List of notable changes:

adds banner to recipe
removes automatic horizontal alignment between page heading and first input, as the banner now takes up too much vertical space to make this feasible.

What should reviewers focus on?

Review the design and storybook and check we're happy with the outcome

Steps to test:

Open this storybook story to see the default form version
Open this storybook story to see the extended, Enterprise version of the form.

Supporting resources (related issues, external links, etc):

Design

Contributor checklist:

[ ] All new and existing CI checks pass
[ ] Tests prove that the feature works and covers both happy and unhappy paths
[ ] Any drop in coverage, breaking changes or regressions have been documented above
[ ] New visual snapshots have been generated / updated for any UI changes
[ ] All developer debugging and non-functional logging has been removed
[ ] Related issues have been referenced in the PR description

Reviewer checklist:

[ ] Check that pull request and proposed changes adhere to our contribution guidelines and code of conduct
[ ] Check that tests prove the feature works and covers both happy and unhappy paths
[ ] Check that there aren't other open Pull Requests for the same update/change

Screenshots:

Please try to provide before and after screenshots or videos

 Design  Storybook

Thanks @nsolerieu

One small nice to have: could we align the top of both side's content. The misalignment is very visible now that the top elements have horizontal borders (labels + signin-box)

Fixed 👍
Here's how it looks now...


vercel build error: "No output directory named public"

Not sure why but the vercel build is now breaking and live demo is not reflecting the current code base.
The error in build output:
- Error! No Output Directory named "public" found after the Build completed. You can configure the Output Directory in your Project Settings.

It finished off the error with the message:

Learn More: https://vercel.link/missing-public-directory

Apparently it doesn't like "public" so I need to investigate that.
Vercel build command:
cd ../.. && npx turbo run build --scope=site --include-dependencies --no-deps

here's the full build output for brevity:
[07:59:22.126] Cloning github.com/oneezy/monorepo (Branch: main, Commit: 0e610c4)
[07:59:22.552] Cloning completed: 425.746ms
[07:59:23.533] Looking up build cache...
[07:59:23.795] Build Cache not found
[07:59:24.012] Running "vercel build"
[07:59:24.502] Vercel CLI 28.0.1
[07:59:24.822] Detected `pnpm-lock.yaml` generated by pnpm 7...
[07:59:24.822] Running "install" command: `pnpm i`...
[07:59:25.356] Scope: all 10 workspace projects
[07:59:25.470] ../..                                    | Progress: resolved 1, reused 0, downloaded 0, added 0
[07:59:25.617] ../..                                    | +739 ++++++++++++++++++++++++++++++++
[07:59:26.067] Packages are hard linked from the content-addressable store to the virtual store.
[07:59:26.067]   Content-addressable store is at: /vercel/.local/share/pnpm/store/v3
[07:59:26.068]   Virtual store is at:             ../../node_modules/.pnpm
[07:59:26.475] ../..                                    | Progress: resolved 739, reused 0, downloaded 45, added 39
[07:59:27.475] ../..                                    | Progress: resolved 739, reused 0, downloaded 128, added 129
[07:59:28.476] ../..                                    | Progress: resolved 739, reused 0, downloaded 261, added 262
[07:59:29.477] ../..                                    | Progress: resolved 739, reused 0, downloaded 353, added 357
[07:59:30.478] ../..                                    | Progress: resolved 739, reused 0, downloaded 461, added 465
[07:59:31.486] ../..                                    | Progress: resolved 739, reused 0, downloaded 592, added 594
[07:59:32.487] ../..                                    | Progress: resolved 739, reused 0, downloaded 727, added 732
[07:59:33.489] ../..                                    | Progress: resolved 739, reused 0, downloaded 734, added 739, done
[07:59:33.656] .../node_modules/svelte-preprocess postinstall$ echo "[svelte-preprocess] Don't forget to install the preprocessors packages that will be used: node-sass/sass, stylus, less, postcss & postcss-load-config, coffeescript, pug, etc..."
[07:59:33.671] .../node_modules/svelte-preprocess postinstall: [svelte-preprocess] Don't forget to install the preprocessors packages that will be used: node-sass/sass, stylus, less, postcss & postcss-load-config, coffeescript, pug, etc...
[07:59:33.672] .../node_modules/svelte-preprocess postinstall: Done
[07:59:33.682] .../node_modules/svelte-preprocess postinstall$ echo "[svelte-preprocess] Don't forget to install the preprocessors packages that will be used: node-sass/sass, stylus, less, postcss & postcss-load-config, coffeescript, pug, etc..."
[07:59:33.683] .../node_modules/svelte-preprocess postinstall$ echo "[svelte-preprocess] Don't forget to install the preprocessors packages that will be used: node-sass/sass, stylus, less, postcss & postcss-load-config, coffeescript, pug, etc..."
[07:59:33.700] .../node_modules/svelte-preprocess postinstall: [svelte-preprocess] Don't forget to install the preprocessors packages that will be used: node-sass/sass, stylus, less, postcss & postcss-load-config, coffeescript, pug, etc...
[07:59:33.701] .../node_modules/svelte-preprocess postinstall: Done
[07:59:33.701] .../node_modules/svelte-preprocess postinstall: [svelte-preprocess] Don't forget to install the preprocessors packages that will be used: node-sass/sass, stylus, less, postcss & postcss-load-config, coffeescript, pug, etc...
[07:59:33.702] .../node_modules/svelte-preprocess postinstall: Done
[07:59:33.758]<EMAIL_ADDRESS>postinstall$ node install.js
[07:59:33.758]<EMAIL_ADDRESS>postinstall$ node install.js
[07:59:33.836]<EMAIL_ADDRESS>postinstall: Done
[07:59:33.847]<EMAIL_ADDRESS>postinstall: Done
[07:59:33.925] .../node_modules/@sveltejs/kit postinstall$ node svelte-kit.js sync
[07:59:34.001] .../node_modules/@sveltejs/kit postinstall: Missing /vercel/path0/svelte.config.js — skipping
[07:59:34.003] .../node_modules/@sveltejs/kit postinstall: Done
[07:59:34.525]
[07:59:34.525] dependencies:
[07:59:34.526] + @packages/components 0.1.1 <- ../../packages/components
[07:59:34.526] + @packages/config 0.1.0 <- ../../packages/config
[07:59:34.526] + @packages/metadata 0.1.1 <- ../../packages/metadata
[07:59:34.526]
[07:59:34.526] devDependencies:
[07:59:34.526] + @sveltejs/adapter-auto 1.0.0-next.64
[07:59:34.526] + @sveltejs/kit 1.0.0-next.405
[07:59:34.526] + @tailwindcss/typography 0.5.4
[07:59:34.526] + autoprefixer 10.4.8
[07:59:34.526] + eslint 7.32.0
[07:59:34.526] + eslint-config-prettier 8.5.0
[07:59:34.526] + eslint-plugin-svelte3 3.4.1
[07:59:34.527] + mdsvex 0.10.6
[07:59:34.528] + postcss 8.4.16
[07:59:34.528] + postcss-load-config 3.1.4
[07:59:34.528] + prettier 2.7.1
[07:59:34.528] + prettier-plugin-svelte 2.7.0
[07:59:34.528] + prettier-plugin-tailwindcss 0.1.13
[07:59:34.528] + svelte 3.49.0
[07:59:34.528] + svelte-accessible-accordion 2.1.0
[07:59:34.528] + svelte-check 2.8.0
[07:59:34.528] + svelte-preprocess 4.10.7
[07:59:34.528] + svrollbar 0.12.0
[07:59:34.528] + tailwindcss 3.1.8
[07:59:34.529] + vite 3.0.7
[07:59:34.529]
[07:59:34.529] ../docs preinstall$ pnpm exec inherit -u
[07:59:34.529] ../.. preinstall$ pnpm exec inherit -u
[07:59:34.529] . preinstall$ pnpm exec inherit -u
[07:59:35.369] ../.. preinstall: Nothing needs to be updated.
[07:59:35.379] ../.. preinstall: Done
[07:59:35.380] ../.. prepare$ husky install
[07:59:35.420] ../docs preinstall: Nothing needs to be updated.
[07:59:35.434] ../docs preinstall: Done
[07:59:35.435] ../docs prepare$ svelte-kit sync
[07:59:35.472] ../.. prepare: husky - Git hooks installed
[07:59:35.475] ../.. prepare: Done
[07:59:35.524] . preinstall: Nothing needs to be updated.
[07:59:35.539] . preinstall: Done
[07:59:35.539] . prepare$ svelte-kit sync
[07:59:35.555] ../docs prepare: `svelte-kit sync` now runs on "postinstall" — please remove the "prepare" script from your package.json
[07:59:35.564] ../docs prepare: Done
[07:59:35.632] . prepare: `svelte-kit sync` now runs on "postinstall" — please remove the "prepare" script from your package.json
[07:59:35.635] . prepare: Done
[07:59:36.241] • Packages in scope: @apps/site, @packages/components, @packages/config, @packages/metadata
[07:59:36.241] • Running build in 4 packages
[07:59:36.241] • Remote computation caching enabled
[07:59:36.770] @apps/site:build: cache miss, executing 49a98bfaf1ebefcf
[07:59:37.237] @apps/site:build:
[07:59:37.238] @apps/site:build: ><EMAIL_ADDRESS>build /vercel/path0/apps/site
[07:59:37.238] @apps/site:build: > vite build
[07:59:37.238] @apps/site:build:
[07:59:37.767] @apps/site:build: vite v3.0.7 building for production...
[07:59:37.791] @apps/site:build: transforming...
[07:59:42.574] @apps/site:build: ✓ 80 modules transformed.
[07:59:42.680] @apps/site:build: rendering chunks...
[07:59:42.688] @apps/site:build: The emitted file "_app/immutable/assets/__error-6e692366.css" overwrites a previously emitted file of the same name.
[07:59:42.759] @apps/site:build: .svelte-kit/output/client/manifest.json                                                            5.11 KiB
[07:59:42.763] @apps/site:build: .svelte-kit/output/client/_app/immutable/layout.svelte-c8457e33.js                                 0.53 KiB / gzip: 0.35 KiB
[07:59:42.765] @apps/site:build: .svelte-kit/output/client/_app/immutable/pages/__error.svelte-b0ba7faa.js                          1.01 KiB / gzip: 0.62 KiB
[07:59:42.765] @apps/site:build: .svelte-kit/output/client/_app/immutable/pages/__layout-site.svelte-976e0503.js                    7.47 KiB / gzip: 2.44 KiB
[07:59:42.765] @apps/site:build: .svelte-kit/output/client/_app/immutable/pages/docs/__error.svelte-9d1fd950.js                     1.01 KiB / gzip: 0.62 KiB
[07:59:42.765] @apps/site:build: .svelte-kit/output/client/_app/immutable/pages/docs/__layout-docs.svelte-8a8ff74a.js               7.48 KiB / gzip: 2.44 KiB
[07:59:42.765] @apps/site:build<EMAIL_ADDRESS>                6.30 KiB / gzip: 2.36 KiB
[07:59:42.766] @apps/site:build: .svelte-kit/output/client/_app/immutable/start-42655908.js                                         26.72 KiB / gzip: 9.08 KiB
[07:59:42.766] @apps/site:build<EMAIL_ADDRESS>                     6.65 KiB / gzip: 2.51 KiB
[07:59:42.766] @apps/site:build: .svelte-kit/output/client/_app/immutable/chunks/index-092d6d0a.js                                  0.79 KiB / gzip: 0.49 KiB
[07:59:42.766] @apps/site:build: .svelte-kit/output/client/_app/immutable/chunks/Content-1e902885.js                                3.57 KiB / gzip: 1.69 KiB
[07:59:42.766] @apps/site:build: .svelte-kit/output/client/_app/immutable/chunks/index-0c5168cd.js                                  12.09 KiB / gzip: 5.06 KiB
[07:59:42.766] @apps/site:build<EMAIL_ADDRESS>                          0.35 KiB / gzip: 0.16 KiB
[07:59:42.767] @apps/site:build<EMAIL_ADDRESS>                          0.35 KiB / gzip: 0.16 KiB
[07:59:42.767] @apps/site:build: .svelte-kit/output/client/_app/immutable/chunks/Header.svelte_svelte_type_style_lang-5940fe71.js   27.31 KiB / gzip: 9.06 KiB
[07:59:42.767] @apps/site:build: .svelte-kit/output/client/_app/immutable/assets/__layout-site-2b0fdc58.css                         48.65 KiB / gzip: 6.85 KiB
[07:59:42.767] @apps/site:build: .svelte-kit/output/client/_app/immutable/chunks/global-11ccb3e0.js                                 31.14 KiB / gzip: 9.62 KiB
[07:59:42.767] @apps/site:build: .svelte-kit/output/client/_app/immutable/assets/__error-6e692366.css                               0.31 KiB / gzip: 0.18 KiB
[07:59:42.767] @apps/site:build: .svelte-kit/output/client/_app/immutable/assets/Header-42a7efbb.css                                1.12 KiB / gzip: 0.40 KiB
[07:59:42.767] @apps/site:build: .svelte-kit/output/client/_app/immutable/assets/__layout-docs-7e89b0f4.css                         48.83 KiB / gzip: 6.90 KiB
[07:59:42.767] @apps/site:build: .svelte-kit/output/client/_app/immutable/assets/global-529224ed.css                                55.42 KiB / gzip: 7.94 KiB
[07:59:42.783] @apps/site:build: vite v3.0.7 building SSR bundle for production...
[07:59:42.788] @apps/site:build: transforming...
[07:59:43.869] @apps/site:build: "inview" is imported from external module "svelte-inview" but never used in "../../packages/components/lib/Section/Section.svelte".
[07:59:43.869] @apps/site:build: ✓ 78 modules transformed.
[07:59:43.906] @apps/site:build: Generated an empty chunk: "hooks"
[07:59:43.912] @apps/site:build: The emitted file "_app/immutable/assets/__error-3a3c8c46.css" overwrites a previously emitted file of the same name.
[07:59:43.917] @apps/site:build: rendering chunks...
[07:59:43.942] @apps/site:build: .svelte-kit/output/server/manifest.json                                                            3.45 KiB
[07:59:43.942] @apps/site:build: .svelte-kit/output/server/index.js                                                                 81.29 KiB
[07:59:43.943] @apps/site:build: .svelte-kit/output/server/entries/fallbacks/layout.svelte.js                                       0.25 KiB
[07:59:43.943] @apps/site:build: .svelte-kit/output/server/entries/pages/__error.svelte.js                                          0.80 KiB
[07:59:43.943] @apps/site:build: .svelte-kit/output/server/entries/pages/__layout-site.svelte.js                                    4.75 KiB
[07:59:43.943] @apps/site:build: .svelte-kit/output/server/entries/pages/docs/__error.svelte.js                                     0.80 KiB
[07:59:43.943] @apps/site:build: .svelte-kit/output/server/entries/pages/docs/__layout-docs.svelte.js                               4.76 KiB
[07:59:43.943] @apps/site:build<EMAIL_ADDRESS>                                5.01 KiB
[07:59:43.943] @apps/site:build<EMAIL_ADDRESS>                                     5.15 KiB
[07:59:43.943] @apps/site:build: .svelte-kit/output/server/_app/immutable/chunks/index-0eb912ed.js                                  7.96 KiB
[07:59:43.943] @apps/site:build: .svelte-kit/output/server/_app/immutable/chunks/Header.svelte_svelte_type_style_lang-ca6ea9cd.js   27.45 KiB
[07:59:43.943] @apps/site:build: .svelte-kit/output/server/_app/immutable/chunks/global-1e6ae8b4.js                                 22.20 KiB
[07:59:43.943] @apps/site:build: .svelte-kit/output/server/_app/immutable/chunks/Content-0e0e39e8.js                                2.45 KiB
[07:59:43.944] @apps/site:build: .svelte-kit/output/server/_app/immutable/chunks/hooks-bced8853.js                                  0.00 KiB
[07:59:44.459] @apps/site:build: vite v3.0.7 building for production...
[07:59:44.462] @apps/site:build: transforming...
[07:59:44.468] @apps/site:build: ✓ 2 modules transformed.
[07:59:44.476] @apps/site:build: rendering chunks...
[07:59:44.477] @apps/site:build: .svelte-kit/output/client/service-worker.js   5.23 KiB / gzip: 1.53 KiB
[07:59:44.477] @apps/site:build:
[07:59:44.477] @apps/site:build: Run npm run preview to preview your production build locally.
[07:59:44.508]
[07:59:44.508]  Tasks:    1 successful, 1 total
[07:59:44.508] Cached:    0 cached, 1 total
[07:59:44.508]   Time:    8.299s
[07:59:44.509]
[07:59:45.372] Error! No Output Directory named "public" found after the Build completed. You can configure the Output Directory in your Project Settings.
[07:59:45.372] Learn More: https://vercel.link/missing-public-directory

Did you set the output dir to build on Vercel control panel ?

Just tried that and it resulted to a similar error:
- Error! No Output Directory named "build" found after the Build completed. You can configure the Output Directory in your Project Settings.

I asked about this recently on Sveltekit issue #4755 and got some feedback. Going to play around with some of the suggestions and see if I can get this resolved

Well i just tried everything I could think of and still nothing. Went ahead and reached out to Turborepo's #help channel and created a discord thread
https://discord.com/channels/818588653005176832/1010542993553506324

Fixed from answer given by @madeleineostoja on sveltekit issue #4755.

"FWIW my issue was that I was sharing vite config in a monorepo, and importing { sveltekit } from '@sveltejs/kit/vite' from the shared config rather than the project caused the adapter to not run. Might be worth documenting that that has to be imported from the project root in a monorepo env.
Otherwise this can probably be closed out again, sorry for the false alarm!"

That said, there's still room for this to be improved because I just copied/pasted the shared vite.config to the other as a quick fix.

thought i'd just leave this here since i was having the same issue and this was the first result: if you're using turborepo, don't forget the .vercel/ directory in the build output!
"pipeline": {
  "build": {
    "dependsOn": [...]
-   "outputs": [..., ".svelte-kit/**"],
+   "outputs": [..., ".svelte-kit/**", ".vercel/**"],
    ...
  },
}

thought i'd just leave this here since i was having the same issue and this was the first result: if you're using turborepo, don't forget the .vercel/ directory in the build output!
"pipeline": {
  "build": {
    "dependsOn": [...]
-   "outputs": [..., ".svelte-kit/**"],
+   "outputs": [..., ".svelte-kit/**", ".vercel/**"],
    ...
  },
}

Thanks @nasso ! This was exactly what I needed.


Tool missed catching space after namespace prefix

From Ajai "dc-import also missed on extra space after the
namespace prefix which the presubmit tests caught, like,
measuredProperty: dcid:  receipts"

A few other cases missed by dc-import:

missing comma in properties that include a list:
eg: rangeIncludes: dcid:Class1  dcid:Class2

property name not matching the dcid
eg: Node: dcid:myProp
name: "MyProp"  <-- name should match the dcid for properties (or be omitted)


docs(select component documentation nav link): fix broken link in sel…

…ect api documentation
fix #476
Issue: #
What I did

Screenshots (if appropriate):
Checklist

[x] changeset has been added
[x] I have made corresponding changes to the documentation
[x] New and existing unit tests pass locally with my changes
[ ] I have added tests that prove my fix is effective or that my feature works

How to test

Codecov Report
Base: 86.22% // Head: 86.29% // Increases project coverage by +0.06% :tada:

Coverage data is based on head (cc6feaa) compared to base (9830302).
Patch has no changes to coverable lines.

Additional details and impacted files
@@            Coverage Diff             @@
##              dev     #949      +/-   ##
==========================================
+ Coverage   86.22%   86.29%   +0.06%
==========================================
  Files         175      176       +1
  Lines        4625     4728     +103
  Branches     1581     1629      +48
==========================================
+ Hits         3988     4080      +92
- Misses        324      329       +5
- Partials      313      319       +6

Impacted Files
Coverage Δ

...mponents/FormFieldContainer/FormFieldContainer.tsx
93.75% <0.00%> (-6.25%)
:arrow_down:

...act-magma-dom/src/components/ButtonGroup/index.tsx
74.07% <0.00%> (-5.93%)
:arrow_down:

...agma-dom/src/components/Combobox/MultiCombobox.tsx
91.46% <0.00%> (-1.98%)
:arrow_down:

...ges/react-magma-dom/src/components/Input/index.tsx
100.00% <0.00%> (ø)

...es/react-magma-dom/src/components/Button/index.tsx
100.00% <0.00%> (ø)

.../react-magma-dom/src/components/Combobox/index.tsx
100.00% <0.00%> (ø)

.../react-magma-dom/src/components/Textarea/index.tsx
100.00% <0.00%> (ø)

...react-magma-dom/src/components/InputBase/index.tsx
63.58% <0.00%> (ø)

...ct-magma-dom/src/components/StyledButton/index.tsx
100.00% <0.00%> (ø)

...agma-dom/src/components/Combobox/ComboboxInput.tsx
72.50% <0.00%> (ø)

... and 5 more

Help us with your feedback. Take ten seconds to tell us how you rate us. Have a feature suggestion? Share it here.

:umbrella: View full report at Codecov.
:loudspeaker: Do you have feedback about the report comment? Let us know in this issue.


New package: Stellantis.CitroenUpdate version 1.5.2

[x] Have you signed the Contributor License Agreement?
[x] Have you checked that there aren't other open pull requests for the same manifest update/change?
[x] This PR only modifies one (1) manifest
[x] Have you validated your manifest locally with winget validate --manifest <path>?

[x] Does your manifest conform to the 1.5 schema?

Note: <path> is the name of the directory containing the manifest you're submitting.

Microsoft Reviewers: Open in CodeFlow

https://github.com/microsoft/winget-pkgs/pull/136908#issuecomment-1915410841

Refer to https://github.com/microsoft/winget-pkgs/pull/136908#issuecomment-1915879279

Refer to https://github.com/microsoft/winget-pkgs/pull/136908#issuecomment-1924911142


Release 0.1.0

Release 0.1.0
Bug fixes, minor ui changes and experimental stuff
Closing

[x] #48
[x] #56
[x] #50
[x] #57
[x] #45
[x] #42
[x] #46

New Features

Added Element redesign prototype for better custom element support in juno_custom. Not supported

@DavidDierickx ready

Hello @patrickcleeve2! Thanks for updating this PR. We checked the lines you've touched for PEP 8 issues, and found:

In the file juno/beam.py:

Line 387:80: E501 line too long (180 > 79 characters)

In the file juno/juno_custom/element_template.py:

Line 15:80: E501 line too long (82 > 79 characters)

In the file juno/juno_custom/elements/axicon.py:

Line 26:29: W292 no newline at end of file
Line 26:29: W292 no newline at end of file
Line 26:29: W292 no newline at end of file

In the file juno/juno_custom/elements/focusing.py:

Line 16:1: W293 blank line contains whitespace

In the file juno/juno_custom/elements/lattice.py:

Line 29:80: E501 line too long (86 > 79 characters)
Line 33:80: E501 line too long (91 > 79 characters)
Line 100:80: E501 line too long (81 > 79 characters)
Line 225:80: E501 line too long (82 > 79 characters)
Line 238:80: E501 line too long (88 > 79 characters)
Line 262:80: E501 line too long (95 > 79 characters)

In the file juno/juno_custom/elements/microlens.py:

Line 9:80: E501 line too long (80 > 79 characters)
Line 51:1: W293 blank line contains whitespace
Line 51:1: W391 blank line at end of file

In the file juno/juno_custom/elements/test.py:

Line 16:1: E302 expected 2 blank lines, found 1
Line 38:19: W292 no newline at end of file

In the file juno/juno_custom/main.py:

Line 12:1: E302 expected 2 blank lines, found 1
Line 15:1: W293 blank line contains whitespace
Line 20:10: E111 indentation is not a multiple of four
Line 20:10: E117 over-indented
Line 21:1: W293 blank line contains whitespace
Line 24:1: W293 blank line contains whitespace
Line 25:80: E501 line too long (111 > 79 characters)
Line 28:1: W293 blank line contains whitespace
Line 29:5: E303 too many blank lines (2)
Line 33:80: E501 line too long (86 > 79 characters)
Line 44:80: E501 line too long (101 > 79 characters)
Line 58:13: E117 over-indented
Line 58:80: E501 line too long (82 > 79 characters)
Line 60:1: E302 expected 2 blank lines, found 1
Line 61:1: W293 blank line contains whitespace
Line 65:1: W293 blank line contains whitespace
Line 67:13: E303 too many blank lines (3)
Line 69:1: W293 blank line contains whitespace
Line 70:1: W293 blank line contains whitespace
Line 71:5: E303 too many blank lines (2)
Line 73:1: W293 blank line contains whitespace
Line 74:80: E501 line too long (86 > 79 characters)
Line 76:1: E305 expected 2 blank lines after class or function definition, found 1

In the file juno/juno_custom/tools/beam_tools.py:

Line 14:1: E302 expected 2 blank lines, found 1

In the file juno/juno_custom/tools/element_tools.py:

Line 19:80: E501 line too long (82 > 79 characters)
Line 22:80: E501 line too long (88 > 79 characters)

In the file juno/juno_custom/tools/simulation_tools.py:

Line 34:9: E116 unexpected indentation (comment)
Line 41:80: E501 line too long (82 > 79 characters)
Line 53:80: E501 line too long (86 > 79 characters)
Line 86:80: E501 line too long (80 > 79 characters)

In the file juno/juno_custom/ui/main.py:

Line 33:80: E501 line too long (115 > 79 characters)
Line 53:80: E501 line too long (80 > 79 characters)
Line 54:80: E501 line too long (83 > 79 characters)
Line 60:80: E501 line too long (81 > 79 characters)
Line 78:80: E501 line too long (88 > 79 characters)
Line 79:80: E501 line too long (93 > 79 characters)
Line 80:80: E501 line too long (85 > 79 characters)
Line 81:80: E501 line too long (91 > 79 characters)

In the file juno/juno_custom/user_interface.py:

Line 29:80: E501 line too long (80 > 79 characters)
Line 30:80: E501 line too long (82 > 79 characters)
Line 107:80: E501 line too long (84 > 79 characters)

In the file juno/plotting.py:

Line 656:1: W293 blank line contains whitespace
Line 658:26: E261 at least two spaces before inline comment

In the file juno/run_simulation.py:

Line 13:80: E501 line too long (89 > 79 characters)

In the file juno/ui/BeamCreation.py:

Line 201:40: W291 trailing whitespace
Line 269:80: E501 line too long (92 > 79 characters)

In the file juno/ui/ElementCreation.py:

Line 70:80: E501 line too long (86 > 79 characters)
Line 340:80: E501 line too long (82 > 79 characters)

In the file juno/ui/SimulationSetup.py:

Line 55:80: E501 line too long (87 > 79 characters)
Line 67:80: E501 line too long (91 > 79 characters)
Line 68:80: E501 line too long (91 > 79 characters)
Line 69:1: W293 blank line contains whitespace
Line 71:80: E501 line too long (83 > 79 characters)
Line 72:1: W293 blank line contains whitespace
Line 74:80: E501 line too long (84 > 79 characters)
Line 75:80: E501 line too long (86 > 79 characters)
Line 76:80: E501 line too long (90 > 79 characters)
Line 77:80: E501 line too long (90 > 79 characters)
Line 140:80: E501 line too long (101 > 79 characters)
Line 201:80: E501 line too long (84 > 79 characters)
Line 203:24: W291 trailing whitespace
Line 216:5: E303 too many blank lines (3)
Line 220:80: E501 line too long (86 > 79 characters)
Line 251:80: E501 line too long (84 > 79 characters)

In the file juno/ui/qtdesigner_files/BeamCreation.py:

Line 299:80: E501 line too long (83 > 79 characters)
Line 300:80: E501 line too long (80 > 79 characters)
Line 305:80: E501 line too long (90 > 79 characters)
Line 306:80: E501 line too long (92 > 79 characters)
Line 307:80: E501 line too long (89 > 79 characters)
Line 308:80: E501 line too long (82 > 79 characters)
Line 311:80: E501 line too long (88 > 79 characters)
Line 312:80: E501 line too long (93 > 79 characters)
Line 313:80: E501 line too long (94 > 79 characters)
Line 314:80: E501 line too long (94 > 79 characters)
Line 315:80: E501 line too long (95 > 79 characters)
Line 316:80: E501 line too long (88 > 79 characters)
Line 317:80: E501 line too long (80 > 79 characters)
Line 318:80: E501 line too long (81 > 79 characters)
Line 319:80: E501 line too long (86 > 79 characters)
Line 320:80: E501 line too long (89 > 79 characters)
Line 321:80: E501 line too long (91 > 79 characters)
Line 322:80: E501 line too long (94 > 79 characters)
Line 323:80: E501 line too long (84 > 79 characters)
Line 360:80: E501 line too long (149 > 79 characters)

In the file juno/ui/qtdesigner_files/ElementCreation.py:

Line 98:80: E501 line too long (80 > 79 characters)
Line 101:80: E501 line too long (81 > 79 characters)
Line 263:80: E501 line too long (115 > 79 characters)
Line 300:80: E501 line too long (80 > 79 characters)
Line 301:80: E501 line too long (87 > 79 characters)
Line 302:80: E501 line too long (91 > 79 characters)
Line 303:80: E501 line too long (95 > 79 characters)
Line 304:80: E501 line too long (91 > 79 characters)
Line 305:80: E501 line too long (90 > 79 characters)
Line 306:80: E501 line too long (89 > 79 characters)
Line 307:80: E501 line too long (90 > 79 characters)
Line 308:80: E501 line too long (92 > 79 characters)
Line 309:80: E501 line too long (89 > 79 characters)
Line 310:80: E501 line too long (94 > 79 characters)
Line 311:80: E501 line too long (96 > 79 characters)
Line 312:80: E501 line too long (92 > 79 characters)
Line 313:80: E501 line too long (90 > 79 characters)
Line 314:80: E501 line too long (87 > 79 characters)
Line 315:80: E501 line too long (91 > 79 characters)
Line 316:80: E501 line too long (92 > 79 characters)
Line 317:80: E501 line too long (95 > 79 characters)
Line 318:80: E501 line too long (95 > 79 characters)
Line 319:80: E501 line too long (88 > 79 characters)
Line 320:80: E501 line too long (87 > 79 characters)
Line 321:80: E501 line too long (86 > 79 characters)

In the file juno/ui/qtdesigner_files/JunoLauncher.py:

Line 61:80: E501 line too long (91 > 79 characters)
Line 62:80: E501 line too long (86 > 79 characters)
Line 63:80: E501 line too long (89 > 79 characters)
Line 64:80: E501 line too long (92 > 79 characters)

In the file juno/ui/qtdesigner_files/SimulationSetup.py:

Line 96:80: E501 line too long (112 > 79 characters)
Line 118:80: E501 line too long (87 > 79 characters)
Line 119:80: E501 line too long (82 > 79 characters)
Line 129:80: E501 line too long (115 > 79 characters)
Line 152:80: E501 line too long (81 > 79 characters)
Line 154:80: E501 line too long (81 > 79 characters)
Line 156:80: E501 line too long (82 > 79 characters)
Line 157:80: E501 line too long (93 > 79 characters)
Line 158:80: E501 line too long (85 > 79 characters)
Line 162:80: E501 line too long (86 > 79 characters)
Line 163:80: E501 line too long (81 > 79 characters)
Line 164:80: E501 line too long (91 > 79 characters)
Line 165:80: E501 line too long (84 > 79 characters)
Line 177:80: E501 line too long (115 > 79 characters)
Line 200:80: E501 line too long (94 > 79 characters)
Line 212:80: E501 line too long (91 > 79 characters)
Line 213:80: E501 line too long (106 > 79 characters)
Line 214:80: E501 line too long (103 > 79 characters)
Line 220:80: E501 line too long (88 > 79 characters)
Line 225:80: E501 line too long (96 > 79 characters)
Line 226:80: E501 line too long (80 > 79 characters)
Line 232:80: E501 line too long (81 > 79 characters)
Line 234:80: E501 line too long (88 > 79 characters)
Line 236:80: E501 line too long (118 > 79 characters)
Line 237:80: E501 line too long (87 > 79 characters)
Line 238:80: E501 line too long (95 > 79 characters)
Line 239:80: E501 line too long (110 > 79 characters)
Line 240:80: E501 line too long (102 > 79 characters)
Line 241:80: E501 line too long (102 > 79 characters)
Line 243:80: E501 line too long (100 > 79 characters)

In the file juno/ui/qtdesigner_files/VisualiseResults.py:

Line 146:80: E501 line too long (89 > 79 characters)
Line 147:80: E501 line too long (81 > 79 characters)
Line 148:80: E501 line too long (83 > 79 characters)
Line 149:80: E501 line too long (86 > 79 characters)
Line 150:80: E501 line too long (87 > 79 characters)
Line 151:80: E501 line too long (84 > 79 characters)
Line 152:80: E501 line too long (91 > 79 characters)
Line 153:80: E501 line too long (92 > 79 characters)
Line 154:80: E501 line too long (82 > 79 characters)
Line 155:80: E501 line too long (94 > 79 characters)


Feature request: kill the active window

killactive actually just closes a window.
I know that there is hyprctl kill maybe is possible to use that with the window id or something.

you can create a custom script that does this.
#!/bin/sh

pid=$(hyprctl activewindow -j | jq '.pid')
kill $pid

place this in the ~/.config/hypr/scripts/killactive
dont forget to chage your binding, ex;
$mainMod = SUPER
bind = $mainMod, q, sh ~/.config/hypr/scripts/killactive,

If you don't have/want jq:
kill $(hyprctl activewindow | grep "pid:" | awk -F ':' '{ print $2 }')

so it works, close the issue?

I think that it would be nice to have this as a built-in feature.

I think that it would be nice to have this as a built-in feature.

I wonder if you can kill only the active one.

you can't because that's how computers work.


Show query result value

What would you like to be added:
Currently, if the query result isn't in the expected range, only emitting:
[metrics-1] The query result is a failure. Reason: the response is not expected value

it would be nice to emit actual value on the stage log.
Why is this needed:

/label kind/ada

/unassign @nakabonne


Select first unwatched episode when opening a season.

To prevent too much scrolling. :-)

not sure if this was implemented but i think we can close this issue after 10 years 🙂


Feature/#214

User settings repository & interface
user settings service  and interface
User settings  validator
userDto model
Mapper
Notification type enum
Theme enum
added

Descriptionga Closes deb branchizni yozib qo'ying


Support Scala native 0.5, Update deps

This PR adds support for Scala Native 0.5
In doing so it updates:

scala to 2.13.14
cats to 2.12.0
scala-native to 0.5.4
munit to 1.0.0

All of those changes may not have been strictly necessary, but it's what came naturally.
In particular, I'd love to have eyes on the tlVersionIntroduced changes for Scala Native 0.5
resolves https://github.com/typelevel/cats-parse/pull/593
resolves https://github.com/typelevel/cats-parse/pull/589
resolves https://github.com/typelevel/cats-parse/pull/584
resolves https://github.com/typelevel/cats-parse/pull/574

looks good to me, but I'm not an expert on the whole tlVersionIntroduced thing.
Thanks for taking the time to resolve these issues!


⚡ Add Github Pages Website

This a super cool work, it deserve a dedicated website.
I had to duplicate the README.md and move all the content to ./cours for Mkdocs.
The website should be available at: https://SimonThomine.github.io/CoursDeepLearning after the build (you can have a look to my fork version here)

Hi Julien,
Merci beaucoup !
Thank you so much for your kind words and the fantastic suggestion! I'm glad you like the work.
The website is amazing.
Thanks a lot for contributing :)

For ref you can also use JupyterBook for the website which is a little bit nicer (https://jupyterbook.org/), but I didn't have a template ready to go. This course is a good example: https://dmol.pub/index.html


Implement multilang for bot messages

Messages can be in eng and in rus languages

Implement Internationalization for the following packages:

[ ] Reporting
[ ] Notifier
[x] Chat
[ ] API

Moved GetLocalizer method to configuration, so that it can be accessed from other packages easily.
Need to write tests for Chat and API package and recheck whole functionality.


Disabled HTTPS

Hello again,
I receive a ERR_CONNECTION_REFUSED when I try to access pathfinder (Probably because I don't have mod_ssl enabled, and I don't want to enable it, plus I don't have a certificate to use with it)
Is there any way to disable HTTPS in pathfinder ? (I even tried commenting out some rewrite rules but it keeps redirecting me to HTTPS, you probably hardcoded it :/ )
Thanks.

Please check .htaccess https://github.com/exodus4d/pathfinder/blob/master/.htaccess L.10-16. It is not "hardcoded" :). I expect anyone who is installing a copy of Pathfinder to edit this file, to get it to work in his environment.
Using SSL is recommended. Ill add a hint in the wiki. Thanks for reporting.

As I said, I tried commenting the lines but it keeps redirecting me to HTTPS. I even tried REMOVING the .htaccess file and I got redirected to https again...

Did you try removing history or in incognito? It's very possible your browser remembers that it redirects to https.
—
Sent from Mailbox
On Wed, Sep 23, 2015 at 12:05 PM, Sakarias Longhorn
<EMAIL_ADDRESS>wrote:

As I said, I tried commenting the lines but it keeps redirecting me to HTTPS. I even tried REMOVING the .htaccess file and I got redirected to https again...
Reply to this email directly or view it on GitHub:
https://github.com/exodus4d/pathfinder/issues/26#issuecomment-142553151

I cleared my browser's cache, now I just get a ERR_NAME_NOT_RESOLVED, So I created an A RECORD pointing to www (I think that's the cause, correct me If I'm wrong), I'm waiting for the record to be created now, and i'll report after.

Do not remove them. They are necessary, otherwise the Framework can´t redirect URLs back to the index.php. The index.php works as a dispatcher for any Ajax URL that is called.
This is how it works: http://fatfreeframework.com/routing-engine#sample-apache-configuration
There is no "HTTPS (on/off) switch in the config. But yeah changes to the .htaccess need a complete history clean in your browser. And even than i have sometimes problems to get new changes to work. I´ll do a fresh installation (without SSL) this weekend and check it.

Ok, I'll try to get it to work on my end for now,
Also~ In the installation instructions, at the cron tab part, what cron do I need to add exactly ? (I'm not very familiar with cron jobs, and it says to trigger /cron but.. I don't see that folder in the installation folder.)

EDIT Looks like my virtualhost file is the problem...
When I access pathfinder.polaris-industries.com
.htaccess redirects me to www.pathfinder.polaris-industries.com
and I get ERR_NAME_NOT_RESOLVED
000-default.conf

DNS Zones

Ok so, definitely a cache issue, it's working now... well, I can get to the page but it says 500 Internal Error. (white page)

/cron cron is no folder or any physically script that should be triggered by a Cronjob. It is just a virtual URL, known to Pathfinder (like all the other Ajax URLs in this project). You just have to trigger that URL by a cronjob. If you are on a shared hoster and there is no option to configure Cronjobs (check the Admin interface,...) you will probably switch to a 3rd party Cronjob hoster (e.g. https://www.setcronjob.com/) and configure that path as a Cronjob.
The Script that will be executed behind /cron will then decide which other Cronjob should be executed. For example, some Script should run each hour. That means, that the executed Script (/Cron) will poke an other Script every 60th time. You don´t have to worry about this tasks, they are configures in the cron.ini don´t touch them if you dont know what you are doing.
More Information about the Cron-Extension I use:
https://github.com/xfra35/f3-cron

Ok thanks, I'm reading that, so if I understand correctly I need to :
Create a cron.php somewhere in my /www containing

exec('wget -qO- /dev/null [YOUR INSTALLATION]/cron &> /dev/null', $out, $result);
echo "start:";
echo "Returncode: " .$result ."";
echo "Ausgabe des Scripts: " ."";
echo ""; print_r($out);

and add a cron job like so

php-cli -f /var/www/cron.php

Is it correct ? If yes, should I run the script every minute/hours/days ?
Thanks a lot.

No all you have to do is to "simulate" "someone" that calls the URL http://www.[Your Project]/cron every minute. You cant do that with PHP. e.g. an endless loop wont work (time out problem).
So no one wants to call that URL manually :) So you need an other way to trigger that URL. That is usually done by a Cronjob Configuration. There are many ways to do that. A easy way will probably a 3rd party hoster just for that cronjob (see post above).

I added that one

wget -O - http://www.pathfinder.polaris-industries.com/cron/cron.phpx /dev/null 2>&1

cron.phpx is empty btw, is it good enough ?

Everything is working, so when we look at the error.log we can see

Table 'galatea.mapsolarsystems' doesn't exist
So, I just went to phpmyadmin and checked the tables... they were named for example :
invType
mapSolarSystems
(Notice the capital letters), that's why it wasn't working, but I used the table you provided so.. did I do something wrong when I imported the tables ?

Glad it's working now ! Good job and thanks for your patience.

Tables are still broken in 0.0.11 (needs to be renamed to lowercase, I added a note in the wiki)

For many users without cron job knowledge, using third party cron job service is a good choice.
There is another easy-to-use cron job service that may help: https://www.easycron.com.